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公开(公告)号：US08878295B2
公开(公告)日：2014-11-04
申请号：US13086187
申请日：2011-04-13
申请人： Peter J. Hopper , Alexei Sadovnikov , William French , Erika Mazotti , Richard Wendell Foote, Jr. , Punit Bhola , Vladislav Vashchenko
发明人： Peter J. Hopper , Alexei Sadovnikov , William French , Erika Mazotti , Richard Wendell Foote, Jr. , Punit Bhola , Vladislav Vashchenko
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0653 , H01L29/0657 , H01L29/0696 , H01L29/0882 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/66659 , H01L29/66712 , H01L29/66734 , H01L29/7809 , H01L29/7813 , H01L29/7835
摘要： A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening.
摘要翻译： 具有较低导通状态漏极至源极电阻和较高击穿电压的DMOS晶体管利用沿开口侧壁设置的倾斜超结漂移结构，漏极区位于开口底部和源极区 靠近开口顶部。
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公开(公告)号：US08524548B2
公开(公告)日：2013-09-03
申请号：US13094645
申请日：2011-04-26
申请人： William French , Vladislav Vashchenko , Richard Wendell Foote, Jr. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
发明人： William French , Vladislav Vashchenko , Richard Wendell Foote, Jr. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
IPC分类号： H01L29/66
CPC分类号： H01L29/7824 , H01L21/26586 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66689 , H01L29/7835 , H01L29/78603
摘要： A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.
摘要翻译： 形成在绝缘体上硅（SOI）结构上的横向DMOS晶体具有较高的击穿电压，该击穿电压是由在SOI结构的体区形成的空穴产生的。 空腔暴露SOI结构的绝缘体层的底部表面的一部分，其直接位于DMOS晶体管的漂移区的垂直下方。
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公开(公告)号：US20120273881A1
公开(公告)日：2012-11-01
申请号：US13094645
申请日：2011-04-26
申请人： William French , Vladislav Vashchenko , Richard Wendell Foote, JR. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
发明人： William French , Vladislav Vashchenko , Richard Wendell Foote, JR. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7824 , H01L21/26586 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66689 , H01L29/7835 , H01L29/78603
摘要： A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.
摘要翻译： 形成在绝缘体上硅（SOI）结构上的横向DMOS晶体具有较高的击穿电压，该击穿电压是由在SOI结构的体区形成的空穴产生的。 空腔暴露SOI结构的绝缘体层的底部表面的一部分，其直接位于DMOS晶体管的漂移区的垂直下方。
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公开(公告)号：US20120261753A1
公开(公告)日：2012-10-18
申请号：US13086187
申请日：2011-04-13
申请人： Peter J. Hopper , Alexei Sadovnikov , William French , Erika Mazotti , Richard Wendell Foote, JR. , Punit Bhola , Vladislav Vashchenko
发明人： Peter J. Hopper , Alexei Sadovnikov , William French , Erika Mazotti , Richard Wendell Foote, JR. , Punit Bhola , Vladislav Vashchenko
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0653 , H01L29/0657 , H01L29/0696 , H01L29/0882 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/66659 , H01L29/66712 , H01L29/66734 , H01L29/7809 , H01L29/7813 , H01L29/7835
摘要： A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening.
摘要翻译： 具有较低导通状态漏极至源极电阻和较高击穿电压的DMOS晶体管利用沿开口侧壁设置的倾斜超结漂移结构，漏极区位于开口底部和源极区 靠近开口顶部。
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公开(公告)号：US07714355B1
公开(公告)日：2010-05-11
申请号：US11312704
申请日：2005-12-20
IPC分类号： H01L29/74
CPC分类号： H01L29/7322 , H01L29/0821 , H01L29/74
摘要： In a BSCR or BJT ESD clamp, the breakdown voltage and DC voltage tolerance are controlled by controlling the size of the collector of the BJT device by masking part of the collector.
摘要翻译： 在BSCR或BJT ESD钳位中，通过屏蔽收集器的一部分来控制BJT器件的集电极的尺寸来控制击穿电压和直流电压公差。
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6.发明授权Method of etching a lateral trench under an extrinsic base and improved bipolar transistor 有权在外部基极和改进的双极晶体管之下蚀刻横向沟槽的方法公开(公告)号：US06964907B1
公开(公告)日：2005-11-15
申请号：US10716276
申请日：2003-11-17
IPC分类号： H01L21/302 , H01L21/306 , H01L21/331 , H01L29/04 , H01L29/08 , H01L29/10 , H01L29/732
CPC分类号： H01L21/30608 , H01L29/045 , H01L29/0649 , H01L29/0821 , H01L29/1004 , H01L29/66272 , H01L29/7322
摘要： In a BJT, the extrinsic base to collector capacitance is reduced by forming a lateral trench between the extrinsic base region and collector. This is typically done by using an anisotropic wet etch process in a direction of a orientation wafer.
摘要翻译： 在BJT中，通过在外部基极区域和集电极之间形成横向沟槽来减小外部基极到集电极电容。 这通常通过使用<100>取向晶片的<110>方向的各向异性湿蚀刻工艺来完成。
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公开(公告)号：US07754505B1
公开(公告)日：2010-07-13
申请号：US12284290
申请日：2008-09-19
IPC分类号： H01L21/00
CPC分类号： H01L33/387 , H01L33/04 , H01L33/08
摘要： A silicon-based light emitting structure is formed as a high density array of light-emitting p-n junctions that substantially increases the intensity of the light emitted in a planar region. The p-n junctions are formed using standard CMOS processing methods, and emit light in response to applied voltages that generate avalanche breakdown and an avalanche current.
摘要翻译： 形成硅基发光结构作为发光p-n结的高密度阵列，其显着增加在平坦区域中发射的光的强度。 使用标准CMOS处理方法形成p-n结，并响应于产生雪崩击穿和雪崩电流的施加电压而发光。
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公开(公告)号：US07462874B1
公开(公告)日：2008-12-09
申请号：US11403516
申请日：2006-04-13
IPC分类号： H01L33/00
CPC分类号： H01L33/387 , H01L33/04 , H01L33/08
摘要： A silicon-based light emitting structure is formed as a high density array of light-emitting p-n junctions that substantially increases the intensity of the light emitted in a planar region. The p-n junctions are formed using standard CMOS processing methods, and emit light in response to applied voltages that generate avalanche breakdown and an avalanche current.
摘要翻译： 形成硅基发光结构作为发光p-n结的高密度阵列，其显着增加在平坦区域中发射的光的强度。 使用标准CMOS处理方法形成p-n结，并响应于产生雪崩击穿和雪崩电流的施加电压而发光。
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9.发明申请PHOTODIODE THAT INCORPORATES A CHARGE BALANCED SET OF ALTERNATING N AND P DOPED SEMICONDUCTOR REGIONS 审中-公开包含N和P多个半导体区域的充电平衡组的光电公开(公告)号：US20120326260A1
公开(公告)日：2012-12-27
申请号：US13165050
申请日：2011-06-21
CPC分类号： H01L31/103 , H01L31/03529 , Y02E10/50
摘要： A photodiode comprises a first terminal formed in a surface of a semiconductor substrate; a second terminal formed in the substrate surface and spaced apart from the first terminal; and a plurality of adjacent alternating N-type and P-type diffusion regions formed in the substrate surface between the first terminal and the second terminal.
摘要翻译： 光电二极管包括形成在半导体衬底的表面中的第一端子; 形成在所述基板表面中并与所述第一端子间隔开的第二端子; 以及形成在第一端子和第二端子之间的衬底表面中的多个相邻的交替的N型和P型扩散区域。
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10.发明授权公开(公告)号：US08324603B2
公开(公告)日：2012-12-04
申请号：US12862136
申请日：2010-08-24
CPC分类号： G02B6/43 , G02B6/12004 , G02B6/136 , Y10T29/49155
摘要： Methods and structures provide galvanic isolation for electrical systems using a wide oxide filled trench, and that allows power across the system divide with a transformer, and that transmits data at a high baud rate using an optical link. The system solution allows the integration of all of these elements onto a single semiconductor substrate in contrast to currently available galvanic isolation systems that require multiple individual silicon die that are connected by wire bonds and are relatively slow.
摘要翻译： 方法和结构为使用宽氧化物填充沟槽的电气系统提供电流隔离，并且允许跨系统的功率与变压器分压，并且使用光链路以高波特率传输数据。 与目前可用的电隔离系统相比，该系统解决方案允许将所有这些元件集成到单个半导体衬底上，该电隔离系统需要通过引线键连接并且相对较慢的多个单独的硅管芯。
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