公开(公告)号：US12237236B2

公开(公告)日：2025-02-25

申请号：US18005418

申请日：2021-07-15

Applicant: VueReal Inc.

Inventor： Gholamreza Chaji ,  Ehsanollah Fathi ,  Hossein Zamani Siboni ,  David Hwang

IPC: H01L21/66 ,  G01R1/04 ,  H01L23/28 ,  H01L23/48 ,  H01L29/15

Abstract: The present invention relates to the inspection process which includes providing access to the microdevice contacts, measuring the microdevice and analyzing the data to identify defects or performance of the micro device. The invention also relates to the forming of test electrodes on microdevices. The test electrodes may be connected to hidden contacts. The type of microdevices may be vertical, lateral or a flip chip.

公开(公告)号：US12068428B2

公开(公告)日：2024-08-20

申请号：US16998455

申请日：2020-08-20

Applicant: VueReal Inc.

Inventor： Gholamreza Chaji ,  Ehsanollah Fathi ,  Hossein Zamani Siboni

IPC: H01L33/00 ,  H01L27/15 ,  H01L33/62

CPC classification number: H01L33/0037 ,  H01L27/153 ,  H01L33/62

Abstract: A vertical current mode solid state device comprising a connection pad and side walls comprising a metal-insulator-semiconductor (MIS) structure, wherein leakage current effect of the vertical device is limited through the side walls by biasing the MIS structure.

公开(公告)号：US20200381582A1

公开(公告)日：2020-12-03

申请号：US16998455

申请日：2020-08-20

Applicant: VueReal Inc.

Inventor： Gholamreza Chaji ,  Ehsanollah Fathi ,  Hossein Zamani Siboni

IPC: H01L33/00 ,  H01L27/15 ,  H01L33/62

Abstract: A vertical current mode solid state device comprising a connection pad and side walls comprising a metal-insulator-semiconductor (MIS) structure, wherein leakage current effect of the vertical device is limited through the side walls by biasing the MIS structure.

公开(公告)号：US20240379897A1

公开(公告)日：2024-11-14

申请号：US18779475

申请日：2024-07-22

Applicant: VueReal Inc.

Inventor： Gholamreza Chaji ,  Ehsanollah Fathi ,  Hossein Zamani Siboni

IPC: H01L33/00 ,  H01L25/16 ,  H01L27/15 ,  H01L29/40 ,  H01L29/423 ,  H01L33/20 ,  H01L33/44

Abstract: A micro device structure comprising at least part of an edge of a micro device is covered with a metal-insulator-semiconductor (MIS) structure, wherein the MIS structure comprises a MIS dielectric layer and a MIS gate conductive layer, at least one gate pad provided to the MIS gate conductive layer, and at least one micro device contact extended upwardly on a top surface of the micro device.

公开(公告)号：US20230178528A1

公开(公告)日：2023-06-08

申请号：US18161318

申请日：2023-01-30

Applicant: VueReal Inc.

Inventor： Gholamreza Chaji ,  Ehsanollah Fathi ,  Bahareh Sadeghimakki ,  Hossein Zamani Siboni

IPC: H01L25/075 ,  H01L27/12 ,  H01L33/50 ,  H01L33/62 ,  H01L33/60

CPC classification number: H01L25/0753 ,  H01L27/1214 ,  H01L33/505 ,  H01L33/62 ,  H01L33/60 ,  H01L2933/0066 ,  H01L2933/0041 ,  H01L2933/0058

Abstract: An integrated optical display system includes a backplane with appropriate electronics, and an array of micro-devices. A touch sensing structure may be integrated into the system. In one embodiment, an integrated circuit and system is integrated on top of micro-devices transferred to a substrate. Openings in a planarization layer (or layers) may be provided to connect the micro-devices with electrodes and other circuitry. Light reflectors may be used to redirect the light, and color conversion layers or color filters may be integrated before the micro-devices or on the substrate surface opposite to the surface of micro-devices.

公开(公告)号：US20190288156A1

公开(公告)日：2019-09-19

申请号：US16428103

申请日：2019-05-31

Applicant: VueReal Inc.

Inventor： Gholamreza Chaji ,  Hossein Zamani Siboni ,  Ehsanollah Fathi

IPC: H01L33/00 ,  H01L29/423 ,  H01L25/16 ,  H01L29/40

Abstract: A microdevice structure comprising at least part of an edge of a microdevice is covered with a metal-insulator-semiconductor (MIS) structure, wherein the MIS structure comprises a MIS dielectric layer and a MIS gate conductive layer, at least one gate pad provided to the MIS gate conductive layer, and at least one micro device contact extended upwardly on a top surface of the micro device.

公开(公告)号：US20230055752A1

公开(公告)日：2023-02-23

申请号：US18047903

申请日：2022-10-19

Applicant: VueReal Inc.

Inventor： Gholamreza Chaji ,  Ehsanollah Fathi ,  Yunhan Li ,  Hossein Zamani Siboni

IPC: H01L33/62 ,  H01L33/00 ,  H01L33/38

Abstract: Methods and structures are disclosed for highly efficient vertical devices. The vertical device comprising a plurality of planar active layers formed on a substrate, at least one of a top layer of the plurality of the layers is formed as a plurality of nano-pillars and a passivation layer formed on a space between the plurality of the nanopillars.

公开(公告)号：US10784398B2

公开(公告)日：2020-09-22

申请号：US15389728

申请日：2016-12-23

Applicant: VueReal Inc.

Inventor： Gholamreza Chaji ,  Ehsanollah Fathi ,  Hossein Zamani Siboni

IPC: H01L33/00 ,  H01L33/62 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/15

Abstract: A vertical current mode solid state device comprising a connection pad and side walls comprising a metal-insulator-semiconductor (MIS) structure, wherein leakage current effect of the vertical device is limited through the side walls by biasing the MIS structure.

公开(公告)号：US20200013761A1

公开(公告)日：2020-01-09

申请号：US16542026

申请日：2019-08-15

Applicant: VueReal Inc.

Inventor： Gholamreza Chaji ,  Ehsanollah Fathi ,  Bahareh Sadeghimakki ,  Hossein Zamani Siboni

IPC: H01L25/075 ,  H01L27/12 ,  H01L33/50 ,  H01L33/60 ,  H01L33/62

Abstract: An integrated optical display system includes a backplane with appropriate electronics, and an array of micro-devices. A touch sensing structure may be integrated into the system. In one embodiment, an integrated circuit and system is integrated on top of micro-devices transferred to a substrate. Openings in a planarization layer (or layers) may be provided to connect the micro-devices with electrodes and other circuitry. Light reflectors may be used to redirect the light, and color conversion layers or color filters may be integrated before the micro-devices or on the substrate surface opposite to the surface of micro-devices.

公开(公告)号：US20240250230A1

公开(公告)日：2024-07-25

申请号：US18596923

申请日：2024-03-06

Applicant: VueReal Inc.

Inventor： Gholamreza Chaji ,  Ehsanollah Fathi ,  Yunhan Li ,  Hossein Zamani Siboni

IPC: H01L33/62 ,  H01L33/00 ,  H01L33/38

CPC classification number: H01L33/62 ,  H01L33/0075 ,  H01L33/385

Abstract: Methods and structures are disclosed for highly efficient vertical devices. The vertical device comprising a plurality of planar active layers formed on a substrate, at least one of a top layer of the plurality of the layers is formed as a plurality of nano-pillars and a passivation layer formed on a space between the plurality of the nanopillars.