公开(公告)号：US20130343115A1

公开(公告)日：2013-12-26

申请号：US13601209

申请日：2012-08-31

Applicant: WEI-CHIH CHIEN ,  MING-HSIU LEE

Inventor： WEI-CHIH CHIEN ,  MING-HSIU LEE

IPC: H01L47/00 ,  G11C11/00

CPC classification number: H01L45/08 ,  G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C29/50008 ,  G11C2029/5002 ,  G11C2213/72 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/146

Abstract: A resistance memory cell is provided and includes a first electrode, a tungsten metal layer, a metal oxide layer, and a second electrode. The tungsten metal layer is disposed on the first electrode. The metal oxide layer is disposed on the tungsten metal layer. The second electrode includes a first connection pad, a second connection pad, and a bridge portion electrically connected between the first connection pad and the second connection pad. The bridge portion is disposed on the metal oxide layer or surrounds the metal oxide layer. The resistance memory cell adjusts a resistivity of the metal oxide layer through a first current path, passing through the metal oxide layer and the tungsten metal layer, or a second current path extending from the first connection pad to the second connection pad.

Abstract translation: 提供了一种电阻记忆单元，包括第一电极，钨金属层，金属氧化物层和第二电极。 钨金属层设置在第一电极上。 金属氧化物层设置在钨金属层上。 第二电极包括第一连接焊盘，第二连接焊盘和电连接在第一连接焊盘和第二连接焊盘之间的桥接部分。 桥接部分设置在金属氧化物层上或围绕金属氧化物层。 电阻存储单元通过穿过金属氧化物层和钨金属层的第一电流路径或从第一连接焊盘延伸到第二连接焊盘的第二电流路径来调节金属氧化物层的电阻率。

公开(公告)号：US20130094273A1

公开(公告)日：2013-04-18

申请号：US13706001

申请日：2012-12-05

Applicant: WEI-CHIH CHIEN ,  MING-HSIU LEE ,  HSIANG-LAN LUNG

Inventor： WEI-CHIH CHIEN ,  MING-HSIU LEE ,  HSIANG-LAN LUNG

IPC: G11C5/06

CPC classification number: G11C5/06 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2454 ,  H01L27/249 ,  H01L28/24 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1633

Abstract: A 3D memory device is based on an array of conductive pillars and a plurality of patterned conductor planes including left side and right side conductors adjacent the conductive pillars at left side and right side interface regions. Memory elements in the left side and right side interface regions comprise a programmable transition metal oxide which can be characterized by built-in self-switching behavior, or other programmable resistance material. The conductive pillars can be selected using two-dimensional decoding, and the left side and right side conductors in the plurality of planes can be selected using decoding on a third dimension, combined with left and right side selection.

Abstract translation: 3D存储器件基于导电柱阵列和多个图案化的导体平面，其包括在左侧和右侧界面区域处邻近导电柱的左侧和右侧导体。 左侧和右侧界面区域中的存储元件包括可以通过内置自切换行为表征的可编程过渡金属氧化物或其它可编程电阻材料。 可以使用二维解码来选择导电柱，并且可以使用与左侧和右侧选择相结合的第三维度上的解码来选择多个平面中的左侧和右侧导体。

公开(公告)号：US20100148142A1

公开(公告)日：2010-06-17

申请号：US12332837

申请日：2008-12-11

Applicant: WEI-CHIH CHIEN ,  Kuo-Pin Chang ,  Yi-Chou Chen ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

Inventor： WEI-CHIH CHIEN ,  Kuo-Pin Chang ,  Yi-Chou Chen ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC: H01L21/329 ,  H01L45/00

CPC classification number: G11C17/16 ,  H01L27/101 ,  H01L27/1021

Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein includes a first electrode and a second electrode. The memory device further includes a diode and an anti-fuse metal-oxide memory element comprising aluminum oxide and copper oxide. The diode and the metal-oxide memory element are arranged in electrical series between the first electrode and the second electrode.

Abstract translation: 描述存储器件以及制造方法。 如本文所述的存储器件包括第一电极和第二电极。 存储器件还包括二极管和包含氧化铝和氧化铜的抗熔丝金属氧化物存储元件。 二极管和金属氧化物存储元件电连接在第一电极和第二电极之间。