公开(公告)号：US20210335421A1

公开(公告)日：2021-10-28

申请号：US17226052

申请日：2021-04-08

Applicant: Winbond Electronics Corp.

Inventor： Lih-Wei Lin ,  Lung-Chi Cheng ,  Ju-Chieh Cheng ,  Ying-Shan Kuo

IPC: G11C13/00

Abstract: A resistive memory storage apparatus including a memory cell, a selecting transistor and a memory controller is provided. The memory cell outputs a writing current during a writing pulse width period. The selecting transistor is coupled to the memory cell. The memory controller is coupled to the selecting transistor and the memory cell. The memory controller is configured to apply a control voltage that gradually changes to a predetermined voltage level to a control end of the selecting transistor during a resistance transition phase of the writing pulse width period and set the control voltage to the predetermined voltage level during a filament stabilization phase after the resistance transition phase, so as to limit the writing current to a predetermined current value. In addition, an operating method for a resistive memory storage apparatus is also provided.

公开(公告)号：US10468100B1

公开(公告)日：2019-11-05

申请号：US16046966

申请日：2018-07-26

Applicant: Winbond Electronics Corp.

Inventor： Lih-Wei Lin ,  Yu-An Chen ,  Guan-Yi Li ,  Hsuan-Pao Tseng

IPC: G11C13/00 ,  H01L45/00

Abstract: The disclosure provides a detecting method for a resistive random access memory (RRAM) cell. The method includes: retrieving an RRAM cell and measuring a cell current of the RRAM cell; when a current value of the cell current is higher than a first threshold, performing at least one of a plurality of reset operations and a set operation to the RRAM cell and determining whether a resistance state of the RRAM cell has been switched after experiencing the at least one of the reset operations and the set operation. If no, a recovery operation is performed to the RRAM cell to recover the RRAM cell; if yes, the RRAM is determined to be in a healthy state.

公开(公告)号：US20210303397A1

公开(公告)日：2021-09-30

申请号：US16831828

申请日：2020-03-27

Applicant: Winbond Electronics Corp.

Inventor： Lih-Wei Lin ,  Tsung-Huan Tsai ,  Chi-Shun Lin

IPC: G06F11/10 ,  H03M13/45

Abstract: A memory storage device including a memory storage array and a memory controller is provided. The memory storage array is configured to store data. The memory controller is coupled to the memory storage array. The memory controller is configured to write to-be-written data to the memory storage array. The to-be-written data includes a plurality of data bits and a flip bit. The memory controller performs a verification operation on the to-be-written data to determine whether the data bits includes error bits and records information of the error bits. The memory controller, determines, according to a quantity of the error bits, whether to invert parities of the data bits and the flip bit, and records the parity of the flip bit. In addition, a data access method is also provided.

公开(公告)号：US10978149B1

公开(公告)日：2021-04-13

申请号：US16872374

申请日：2020-05-12

Applicant: Winbond Electronics Corp.

Inventor： Ju-Chieh Cheng ,  Ying-Shan Kuo ,  Lih-Wei Lin ,  Lung-Chi Cheng

IPC: G11C13/00

Abstract: A resistive memory apparatus and an adjusting method for write-in voltage thereof are provided. The adjusting method for write-in voltage includes: selecting an under test memory cell array in a resistive memory; performing N reset operations on a plurality of memory cells of the under test memory cell array according to a reset voltage, and performing N set operations on the memory cells of the under test memory cell array according to a set voltage, wherein n is an integer greater than 1; calculating a reset time variation rate of the reset operations and a set time variation rate of the set operations; and adjusting a voltage value of one of the set voltage and the reset voltage according to the reset time variation rate and the set time variation rate.

公开(公告)号：US10783962B2

公开(公告)日：2020-09-22

申请号：US16105991

申请日：2018-08-21

Applicant: Winbond Electronics Corp.

Inventor： Lih-Wei Lin ,  Lung-Chi Cheng ,  Min-Yen Liu ,  Huan-Ming Chiang

IPC: G11C13/00 ,  H01L45/00

Abstract: A writing method of a resistive memory storage apparatus includes: applying one of a set voltage and a reset voltage serving as a first selected voltage to a memory cell and obtaining a first read current; applying a disturbance voltage to the memory cell and obtaining a second read current; and determining whether a relationship between the first and second read currents satisfies a preset relationship, and if not, applying the other of the set voltage and the reset voltage serving as a second selected voltage to the memory cell and applying the first selected voltage to the memory cell again. A polarity of the disturbance voltage is different from that of the first selected voltage, and the absolute value of the disturbance voltage is less than that of the second selected voltage. A resistive memory storage apparatus is also provided.

公开(公告)号：US20190074059A1

公开(公告)日：2019-03-07

申请号：US16105991

申请日：2018-08-21

Applicant: Winbond Electronics Corp.

Inventor： Lih-Wei Lin ,  Lung-Chi Cheng ,  Min-Yen Liu ,  Huan-Ming Chiang

IPC: G11C13/00 ,  H01L45/00

Abstract: A writing method of a resistive memory storage apparatus includes: applying one of a set voltage and a reset voltage serving as a first selected voltage to a memory cell and obtaining a first read current of the memory cell; applying a disturbance voltage to the memory cell and obtaining a second read current of the memory cell; and determining whether a relationship between the first and second read currents satisfies a preset relationship, and if not, applying the other of the set voltage and the reset voltage serving as a second selected voltage to the memory cell and applying the first selected voltage to the memory cell again. A polarity of the disturbance voltage is different from that of the second selected voltage, and the absolute value of the disturbance voltage is less than that of the second selected voltage. A resistive memory storage apparatus is also provided.

公开(公告)号：US20190172535A1

公开(公告)日：2019-06-06

申请号：US16177460

申请日：2018-11-01

Applicant: Winbond Electronics Corp.

Inventor： Lih-Wei Lin ,  Yu-Cheng Chuang ,  Sung-Yi Lee

IPC: G11C13/00

Abstract: A resistive memory apparatus including a memory cell array and a voltage selector circuit is provided. The memory cell array includes a plurality of memory cells. The voltage selector circuit is coupled to the memory cell array. The voltage selector circuit performs a voltage applying operation on the memory cells via a plurality of different signal transmission paths. Each of the signal transmission paths passes one of the memory cells. IR drops of two of the signal transmission paths are substantially identical, and signal transmission directions thereof are different. In addition, an operating method of a resistive memory apparatus is also provided.

公开(公告)号：US20190057738A1

公开(公告)日：2019-02-21

申请号：US16048350

申请日：2018-07-30

Applicant: Winbond Electronics Corp.

Inventor： Lih-Wei Lin ,  Ju-Chieh Cheng ,  Tsung-Huan Tsai ,  I-Hsien Tseng

IPC: G11C13/00

Abstract: A writing method of a resistive memory storage apparatus is provided. The writing method includes: applying a first set voltage on a memory cell, and acquiring a first reading current of the memory cell; applying a first disturbance voltage on the memory cell, and acquiring a second reading current of the memory cell; and determining to apply a second set voltage or a second disturbance voltage on the memory cell according to a magnitude relationship between the first reading current and the second reading current. An absolute value of the first disturbance voltage is smaller than an absolute value of a reset voltage, and an absolute value of the second disturbance voltage is smaller than an absolute value of the second set voltage. In addition, a resistive memory storage apparatus is also provided.

公开(公告)号：US09627059B2

公开(公告)日：2017-04-18

申请号：US14977667

申请日：2015-12-22

Applicant: Winbond Electronics Corp.

Inventor： Lih-Wei Lin ,  I-Hsien Tseng ,  Ju-Chieh Cheng ,  Chia-Hung Lin ,  Tsung-Huan Tsai ,  Po-Wei Huang

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2213/79 ,  G11C2213/82

Abstract: A resistive memory and a data writing method for a resistive memory cell thereof are provided. The method includes: receiving and decoding a column address signal for generating a decoded result, and providing a word line voltage to a word line of the resistive memory cell; providing a constant current to one of a bit line and a source line of the resistive memory cell, and coupling a reference ground voltage to another one of the bit line and the source line of the resistive memory cell.

公开(公告)号：US09620208B2

公开(公告)日：2017-04-11

申请号：US15190569

申请日：2016-06-23

Applicant: Winbond Electronics Corp.

Inventor： Lih-Wei Lin ,  Tsung-Huan Tsai ,  Chia-Hung Lin ,  I-Hsien Tseng ,  Ju-Chieh Cheng

IPC: G11C11/00 ,  G11C13/00 ,  G11C5/14

CPC classification number: G11C13/0069 ,  G11C5/147 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0045 ,  G11C2013/0066

Abstract: A memory-programming device includes a voltage generator, a resistive random-access memory, a current detector, and a controller. The voltage generator is configured to generate a program voltage. The resistive random-access memory receives the program voltage to generate a program current. The current detector detects the program current. The controller executes a program procedure. The program procedure includes: gradually ramping up the program voltage by the voltage generator and detecting the program current by the current detector; discovering the maximum of the program current to be a reference current; continuing to ramp up the program voltage by the voltage generator and determining whether the program current detected by the current detector is not less than the reference current; controlling the voltage generator to stop generating the program voltage when the program current is not less than the reference current.