公开(公告)号：US20070170521A1

公开(公告)日：2007-07-26

申请号：US11306827

申请日：2006-01-12

申请人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

发明人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211

摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

公开(公告)号：US20070127172A1

公开(公告)日：2007-06-07

申请号：US11275058

申请日：2005-12-06

申请人： Wagdi Abadeer ,  James Adkisson ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Michael Hauser ,  Jed Rankin ,  William Tonti

发明人： Wagdi Abadeer ,  James Adkisson ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Michael Hauser ,  Jed Rankin ,  William Tonti

IPC分类号： H02H9/00

CPC分类号： H01L23/5256 ,  H01L23/525 ,  H01L27/14609 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i.e., replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad once the packaged chip is placed in system. No additional pins on the package are necessary.

摘要翻译： 公开了通过光谱选择的外部光激活通过芯片嵌入式光电二极管的激活以及相应的结构和电路来执行诸如定影操作之类的电功能的方法。 本发明基于将具有特定强度/波长特性的入射光结合到集成电路的附加电路元件，执行维修的实现，即用冗余电路替换故障电路元件以获得和/或可靠性。 一旦封装的芯片放置在系统中，也可以将ESD保护装置从输入焊盘断开。 不需要额外的引脚。

公开(公告)号：US20050090049A1

公开(公告)日：2005-04-28

申请号：US10991936

申请日：2004-11-18

申请人： Wagdi Abadeer ,  Jeffrey Brown ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

发明人： Wagdi Abadeer ,  Jeffrey Brown ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/42368 ,  H01L29/66689 ,  H01L29/7816

摘要： A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI. The drain region is positioned further from the gate than the source region.

公开(公告)号：US20070284659A1

公开(公告)日：2007-12-13

申请号：US11844573

申请日：2007-08-24

申请人： Wagdi Abadeer ,  Jeffrey Brown ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

发明人： Wagdi Abadeer ,  Jeffrey Brown ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

IPC分类号： H01L29/78

CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/42368 ,  H01L29/66689 ,  H01L29/7816

摘要： A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI. The drain region is positioned further from the gate than the source region.

摘要翻译： 公开了一种用于晶体管的方法和结构，该晶体管具有栅极，栅极下方的沟道区，沟道区一侧的源极区，与源极区沟道区相反侧的漏极区，浅沟槽 在漏极区和沟道区之间的衬底中的隔离（STI）区，以及在STI区之下的漏极延伸。 漏极延伸沿着STI区域的底部并沿着STI的边的一部分定位。 沿着STI底部的漏极延伸部分可以包括不同于沿着STI侧面的漏极延伸部分的掺杂剂注入。 沿着STI侧面的排水延伸部分从STI的底部延伸到部分沿着STI侧面的位置。 STI区域位于栅极的一部分之下。 漏极延伸部在漏极区域和围绕STI的下周边的沟道区域之间提供导电路径。 漏极区域比源极区域更靠近栅极定位。

公开(公告)号：US20070284669A1

公开(公告)日：2007-12-13

申请号：US11838934

申请日：2007-08-15

申请人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

发明人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

IPC分类号： H01L29/76

CPC分类号： B07C5/344 ,  G01R31/2831

摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

公开(公告)号：US20060220174A1

公开(公告)日：2006-10-05

申请号：US11440199

申请日：2006-05-24

申请人： Jeffrey Brown ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

发明人： Jeffrey Brown ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

IPC分类号： H01L29/00

CPC分类号： H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Standard photolithography is used to pattern and fabricate a final polysilicon wafer imaged structure which is smaller than normal allowable photo-lithographic minimum dimensions. Three different methods are provided to produce such sub-minimum dimension structures, a first method uses a photolithographic mask with a sub-minimum space between minimum size pattern features of the mask, a second method uses a photolithographic mask with a sub-minimum widthwise jog or offset between minimum size pattern features of the mask, and a third method is a combination of the first and second methods. Each of the three methods can be used with three different embodiments, a first embodiment is a polysilicon E-Fuse with a sub-minimum width polysilicon fuse line, a second embodiment is a work function altered/programmed self-aligned MOSFET E-Fuse with a sub-minimum width fuse line, and a third embodiment is a polysilicon MOSFET E-Fuse with a sub-minimum width fuse line which is programmed with a low trigger voltage snapback.

摘要翻译： 使用标准光刻法来图案化和制造最终的多晶硅晶片成像结构，该结构小于正常允许光刻最小尺寸。 提供了三种不同的方法来产生这样的次最小维度结构，第一种方法使用具有掩模的最小尺寸图案特征之间的亚最小空间的光刻掩模，第二种方法使用光刻掩模与次最小宽度方向点动 或掩模的最小尺寸图案特征之间的偏移，第三种方法是第一和第二方法的组合。 三种方法中的每一种可以与三种不同的实施例一起使用，第一实施例是具有亚最小宽度多晶硅熔丝线的多晶硅E熔丝，第二实施例是工作功能改变/编程的自对准MOSFET E-Fuse，具有 亚最小宽度熔丝线，第三实施例是具有低电平触发电压快速编程的亚最小宽度熔丝线的多晶硅MOSFET E-Fuse。

公开(公告)号：US20060060938A1

公开(公告)日：2006-03-23

申请号：US10948773

申请日：2004-09-23

申请人： Wagdi Abadeer ,  John Fifield ,  Robert Gauthier ,  William Tonti

发明人： Wagdi Abadeer ,  John Fifield ,  Robert Gauthier ,  William Tonti

IPC分类号： H01L29/00 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A resettable fuse device is fabricated on one surface of a semiconductor substrate (10) and includes: a gate region (20) having first and second ends; a source node (81) formed in proximity to the first end of the gate region; an extension region (52) formed to connect the source node to the first end of the gate region; and a drain node (80) formed in proximity to the second end of the gate region and separated from the gate region by a distance (D) such that upon application of a predetermined bias voltage to the drain node a connection between the drain node and the second end of the gate region is completed by junction depletion. A gate dielectric (30) and a gate electrode (40) are formed over the gate region. Current flows between the source node and the drain node when the predetermined bias is applied to both the drain node and the gate electrode.

摘要翻译： 在半导体衬底（10）的一个表面上制造可重置熔丝器件，并且包括：具有第一和第二端的栅极区域（20） 源极节点（81），其形成在所述栅极区域的第一端附近; 形成为将源极节点连接到栅极区域的第一端的延伸区域（52） 以及漏极节点（80），其形成在栅极区域的第二端附近，并且与栅极区分离距离（D），使得在向漏极节点施加预定的偏置电压时，漏极节点和 栅极区域的第二端通过结损耗完成。 栅极电介质（30）和栅电极（40）形成在栅极区域上方。 当预定偏压施加到漏极节点和栅电极时，电流在源节点和漏极节点之间流动。

公开(公告)号：US20070241409A1

公开(公告)日：2007-10-18

申请号：US11764571

申请日：2007-06-18

申请人： Toshiharu Furukawa ,  Robert Gauthier ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

发明人： Toshiharu Furukawa ,  Robert Gauthier ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/76237 ,  H01L21/26533 ,  H01L21/76213 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823878 ,  H01L27/0921 ,  H01L29/1087 ,  H01L29/78

摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.

摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 该半导体结构包括成形修饰的隔离区，其形成在通常在制造本体CMOS器件的衬底的两个掺杂阱之间的沟槽中。 成形改进的隔离区域可以包括沟槽的加宽的电介质填充部分，其可以可选地包括分隔两个掺杂阱之间的损伤区域的沟槽的附近损伤区域或狭窄的电介质填充部分。 也可以通过在沟槽中的沟槽基底和介电填料之间提供晶格不匹配的层来抑制闩锁。

公开(公告)号：US20070170518A1

公开(公告)日：2007-07-26

申请号：US11340737

申请日：2006-01-26

申请人： Toshiharu Furukawa ,  Robert Gauthier ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

发明人： Toshiharu Furukawa ,  Robert Gauthier ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

IPC分类号： H01L29/76

CPC分类号： H01L21/76237 ,  H01L21/26533 ,  H01L21/76213 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823878 ,  H01L27/0921 ,  H01L29/1087 ,  H01L29/78

摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.

公开(公告)号：US20070158755A1

公开(公告)日：2007-07-12

申请号：US11330689

申请日：2006-01-12

申请人： Shunhua Chang ,  Toshiharu Furukawa ,  Robert Gauthier ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

发明人： Shunhua Chang ,  Toshiharu Furukawa ,  Robert Gauthier ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

IPC分类号： H01L29/76

CPC分类号： H01L27/0921 ,  H01L21/823878

摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a first doped well formed in a substrate of semiconductor material, a second doped well formed in the substrate proximate to the first doped well, and a deep trench defined in the substrate. The deep trench includes sidewalls positioned between the first and second doped wells. A buried conductive region is defined in the semiconductor material bordering the base and the sidewalls of the deep trench. The buried conductive region intersects the first and second doped wells. The buried conductive region has a higher dopant concentration than the first and second doped wells. The buried conductive region may be formed by solid phase diffusion from a mobile dopant-containing material placed in the deep trench. After the buried conductive region is formed, the mobile dopant-containing material may optionally remain in the deep trench.

摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 该结构包括在半导体材料的衬底中形成的第一掺杂阱，在衬底中形成的靠近第一掺杂阱的第二掺杂阱以及限定在衬底中的深沟槽。 深沟槽包括位于第一和第二掺杂阱之间的侧壁。 在与深沟槽的基底和侧壁接壤的半导体材料中限定掩埋导电区域。 埋入的导电区域与第一和第二掺杂阱相交。 掩埋导电区域具有比第一和第二掺杂阱更高的掺杂剂浓度。 掩埋导电区域可以通过从放置在深沟槽中的含有移动掺杂剂的材料的固相扩散形成。 在形成掩埋导电区域之后，含有移动掺杂剂的材料可以任选地保留在深沟槽中。