公开(公告)号：US08680625B2

公开(公告)日：2014-03-25

申请号：US12905579

申请日：2010-10-15

申请人： Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang ,  Ming-Huan Tsai ,  Hsueh-Chang Sung ,  Chun-Fai Cheng

发明人： Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang ,  Ming-Huan Tsai ,  Hsueh-Chang Sung ,  Chun-Fai Cheng

IPC分类号： H01L27/088

CPC分类号： H01L29/165 ,  H01L21/28123 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： An exemplary semiconductor device is described, which includes a semiconductor substrate having an active region and an isolation region. The active region has a first edge which interfaces with the isolation region. A gate structure formed on the semiconductor substrate. A spacer element abuts the gate structure and overlies the first edge. In an embodiment, the isolation region is an STI structure. An epitaxy region may be formed adjacent the spacer. In embodiments, this epitaxy region is facet-free.

摘要翻译： 描述了一种示例性的半导体器件，其包括具有有源区和隔离区的半导体衬底。 有源区域具有与隔离区域相接合的第一边缘。 形成在半导体衬底上的栅极结构。 间隔元件邻接栅极结构并覆盖在第一边缘上。 在一个实施例中，隔离区域是STI结构。 可以在间隔物附近形成外延区域。 在实施例中，该外延区域是无面的。

公开(公告)号：US20120091539A1

公开(公告)日：2012-04-19

申请号：US12905579

申请日：2010-10-15

申请人： Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang ,  Ming-Huan Tsai ,  Hsueh-Chang Sung ,  Chun-Fai Cheng

发明人： Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang ,  Ming-Huan Tsai ,  Hsueh-Chang Sung ,  Chun-Fai Cheng

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/165 ,  H01L21/28123 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： An exemplary semiconductor device is described, which includes a semiconductor substrate having an active region and an isolation region. The active region has a first edge which interfaces with the isolation region. A gate structure formed on the semiconductor substrate. A spacer element abuts the gate structure and overlies the first edge. In an embodiment, the isolation region is an STI structure. An epitaxy region may be formed adjacent the spacer. In embodiments, this epitaxy region is facet-free.

摘要翻译： 描述了一种示例性的半导体器件，其包括具有有源区和隔离区的半导体衬底。 有源区域具有与隔离区域相接合的第一边缘。 形成在半导体衬底上的栅极结构。 间隔元件邻接栅极结构并覆盖在第一边缘上。 在一个实施例中，隔离区域是STI结构。 可以在间隔物附近形成外延区域。 在实施例中，该外延区域是无面的。

公开(公告)号：US08709897B2

公开(公告)日：2014-04-29

申请号：US12956090

申请日：2010-11-30

申请人： Hsueh-Chang Sung ,  Ming-Huan Tsai ,  Hsien-Hsin Lin ,  Chun-Fai Cheng ,  Wei-Han Fan

发明人： Hsueh-Chang Sung ,  Ming-Huan Tsai ,  Hsien-Hsin Lin ,  Chun-Fai Cheng ,  Wei-Han Fan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/165 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour.

摘要翻译： 用于形成高性能应变源极 - 漏极结构的方法包括在衬底上形成栅极结构并且形成靠近栅极结构的凹穴注入区域。 隔板与门结构相邻形成。 干蚀刻形成具有第一轮廓的凹部; 湿蚀刻将凹槽放大到第二轮廓; 并且热蚀刻将凹槽放大到第三轮廓。 然后在具有第三轮廓的凹槽中形成源极 - 漏极结构。

公开(公告)号：US20110254105A1

公开(公告)日：2011-10-20

申请号：US12761949

申请日：2010-04-16

申请人： Chun-Fai Cheng ,  Ka-Hing Fung ,  Han-Ting Tsai ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Hsueh-Chang Sung ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

发明人： Chun-Fai Cheng ,  Ka-Hing Fung ,  Han-Ting Tsai ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Hsueh-Chang Sung ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/28518 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.

摘要翻译： 提供了具有应变通道的半导体器件及其制造方法。 半导体器件具有形成在通道凹槽上的栅电极。 形成在栅电极的相对侧上的第一凹部和第二凹部填充有应力诱导材料。 应力诱导材料延伸到其中源极/漏极延伸部与栅电极的边缘重叠的区域中。 在一个实施例中，通道凹槽和/或第一和第二凹部的侧壁可以沿{111}面平面。

公开(公告)号：US20120132957A1

公开(公告)日：2012-05-31

申请号：US12956090

申请日：2010-11-30

申请人： Hsueh-Chang Sung ,  Ming-Huan Tsai ,  Hsien-Hsin Lin ,  Chun-Fai Cheng ,  Wei-Han Fan

发明人： Hsueh-Chang Sung ,  Ming-Huan Tsai ,  Hsien-Hsin Lin ,  Chun-Fai Cheng ,  Wei-Han Fan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/165 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour.

摘要翻译： 用于形成高性能应变源极 - 漏极结构的方法包括在衬底上形成栅极结构并且形成靠近栅极结构的凹穴注入区域。 隔板与门结构相邻形成。 干蚀刻形成具有第一轮廓的凹部; 湿蚀刻将凹槽放大到第二轮廓; 并且热蚀刻将凹槽放大到第三轮廓。 然后在具有第三轮廓的凹槽中形成源极 - 漏极结构。

公开(公告)号：US08368147B2

公开(公告)日：2013-02-05

申请号：US12761949

申请日：2010-04-16

申请人： Chun-Fai Cheng ,  Ka-Hing Fung ,  Han-Ting Tsai ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Hsueh-Chang Sung ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

发明人： Chun-Fai Cheng ,  Ka-Hing Fung ,  Han-Ting Tsai ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Hsueh-Chang Sung ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

IPC分类号： H01L21/70

CPC分类号： H01L29/66636 ,  H01L21/28518 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.

摘要翻译： 提供了具有应变通道的半导体器件及其制造方法。 半导体器件具有形成在通道凹槽上的栅电极。 形成在栅电极的相对侧上的第一凹部和第二凹部填充有应力诱导材料。 应力诱导材料延伸到其中源极/漏极延伸部与栅电极的边缘重叠的区域中。 在一个实施例中，通道凹槽和/或第一和第二凹部的侧壁可以沿{111}面平面。

公开(公告)号：US08569139B2

公开(公告)日：2013-10-29

申请号：US12913041

申请日：2010-10-27

申请人： Chun-Feng Nieh ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Yimin Huang ,  Chun-Fai Cheng ,  Han-Ting Tsai ,  Chii-Ming Wu

发明人： Chun-Feng Nieh ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Yimin Huang ,  Chun-Fai Cheng ,  Han-Ting Tsai ,  Chii-Ming Wu

IPC分类号： H01L21/336 ,  H01L21/461

CPC分类号： H01L21/823814 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.

公开(公告)号：US08216906B2

公开(公告)日：2012-07-10

申请号：US12827344

申请日：2010-06-30

申请人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

发明人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/02433 ,  H01L21/02639 ,  H01L21/823814 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a lightly doped source and drain (LDD) region that acts as an etch stop. The LDD region may act as an etch stop during an etching process implemented to form a recess in the substrate that defines a source and drain region of the device.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过形成用作蚀刻停止的轻掺杂源极和漏极（LDD）区域来实现改进的控制。 LDD区域可以在蚀刻工艺期间用作蚀刻停止层，以在衬底中形成限定器件的源极和漏极区域的凹陷。

公开(公告)号：US20120273847A1

公开(公告)日：2012-11-01

申请号：US13543943

申请日：2012-07-09

申请人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

发明人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

IPC分类号： H01L27/085

CPC分类号： H01L21/823807 ,  H01L21/02433 ,  H01L21/02639 ,  H01L21/823814 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit devices. An exemplary integrated circuit device achieved by the method has a surface proximity of about 1 nm to about 3 nm and a tip depth of about 5 nm to about 10 nm. The integrated circuit device having such surface proximity and tip depth includes an epi source feature and an epi drain feature defined by a first facet and a second facet of a substrate in a first direction, such as a {111} crystallographic plane of the substrate, and a third facet of the substrate in a second direction, such as a { 100} crystallographic plane of the substrate.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 通过该方法实现的示例性集成电路器件具有约1nm至约3nm的表面接近度和约5nm至约10nm的尖端深度。 具有这种表面接近度和尖端深度的集成电路器件包括由第一方向（例如衬底的{111}晶体平面）的第一方向上的第一面和第二小面限定的外延源特征和外延漏极特征， 以及在第二方向上的衬底的第三面，例如衬底的{100}晶面。

公开(公告)号：US08445940B2

公开(公告)日：2013-05-21

申请号：US13543943

申请日：2012-07-09

申请人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

发明人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

IPC分类号： H01L31/072

CPC分类号： H01L21/823807 ,  H01L21/02433 ,  H01L21/02639 ,  H01L21/823814 ,  H01L29/7848

摘要： An integrated circuit device is disclosed. The disclosed device provides improved control over a surface proximity and tip depth of integrated circuit devices. An exemplary integrated circuit device disclosed herein has a surface proximity of about 1 nm to about 3 nm and a tip depth of about 5 nm to about 10 nm. The integrated circuit device having such surface proximity and tip depth includes an epi source feature and an epi drain feature defined by a first facet and a second facet of a substrate in a first direction, such as a {111} crystallographic plane of the substrate, and a third facet of the substrate in a second direction, such as a {100} crystallographic plane of the substrate.

摘要翻译： 公开了一种集成电路器件。 所公开的装置提供对集成电路装置的表面接近度和尖端深度的改进的控制。 本文公开的示例性集成电路器件具有约1nm至约3nm的表面接近度和约5nm至约10nm的尖端深度。 具有这种表面接近度和尖端深度的集成电路器件包括由第一方向（例如衬底的{111}晶体平面）的第一方向上的第一面和第二小面限定的外延源特征和外延漏极特征， 以及在第二方向上的衬底的第三面，例如衬底的{100}晶面。