公开(公告)号：US08362804B2

公开(公告)日：2013-01-29

申请号：US12726931

申请日：2010-03-18

申请人： Wen-Hsia Kung ,  Tzuo-Bo Lin ,  Chia-Lung Hung ,  Yu-Pin Chou

发明人： Wen-Hsia Kung ,  Tzuo-Bo Lin ,  Chia-Lung Hung ,  Yu-Pin Chou

IPC分类号： H03K19/0175

CPC分类号： H03K5/151 ,  H03K19/0008

摘要： A differential signal generating device includes a control circuit and a differential signal driver receiving a single-ended signal. The control circuit receives a source signal and generates a control signal corresponding to a first mode when the source signal conforms with a first pre-defined state, and corresponding to a second mode when the source signal conforms with a second pre-defined state. Variations of the source signal are related to signal content of the single-ended signal. The differential signal driver is coupled to the control unit for receiving the control signal therefrom. The differential signal driver outputs a differential signal output according to the single-ended signal when the control signal corresponds to the first mode. The differential signal driver outputs a non-differential signal output when the control signal corresponds to the second mode.

摘要翻译： 差分信号发生装置包括控制电路和接收单端信号的差分信号驱动器。 当源信号符合第一预定义状态时，控制电路接收源信号并产生对应于第一模式的控制信号，并且当源信号符合第二预定义状态时，控制电路对应于第二模式。 源信号的变化与单端信号的信号内容有关。 差分信号驱动器耦合到控制单元以从其接收控制信号。 当控制信号对应于第一模式时，差分信号驱动器根据单端信号输出差分信号。 当控制信号对应于第二模式时，差分信号驱动器输出非差分信号输出。

公开(公告)号：US20100188574A1

公开(公告)日：2010-07-29

申请号：US12692389

申请日：2010-01-22

申请人： Chia-Lung HUNG ,  Tzuo-Bo Lin ,  Hsien-Chun Chang ,  Yu-Pin Chou

发明人： Chia-Lung HUNG ,  Tzuo-Bo Lin ,  Hsien-Chun Chang ,  Yu-Pin Chou

IPC分类号： H04N9/64 ,  H04N5/04

CPC分类号： H04N7/0105 ,  H04N7/0132

摘要： A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.

摘要翻译： 用于控制帧输入和输出的装置和方法被应用于从源设备接收图像数据并将图像数据输出到目的地设备，该设备包括缓冲器，缓冲器控制电路和帧写入控制器。 输入像素时钟不等于输出像素时钟。 帧写入控制器根据输入DE和输出DE生成写许可信号。 缓冲器控制电路根据输入DE和写允许信号产生写控制信号，并根据输出DE生成读控制信号。 缓冲器根据写控制信号和输入像素时钟从源装置接收图像数据，并根据读控制信号和输出像素时钟将图像数据输出到目的地装置。

公开(公告)号：US08471859B2

公开(公告)日：2013-06-25

申请号：US12692389

申请日：2010-01-22

申请人： Chia-Lung Hung ,  Tzuo-Bo Lin ,  Hsien-Chun Chang ,  Yu-Pin Chou

发明人： Chia-Lung Hung ,  Tzuo-Bo Lin ,  Hsien-Chun Chang ,  Yu-Pin Chou

IPC分类号： G09G5/39 ,  G09G5/36 ,  G06F12/02 ,  H04N7/01

CPC分类号： H04N7/0105 ,  H04N7/0132

摘要： A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.

摘要翻译： 用于控制帧输入和输出的装置和方法被应用于从源设备接收图像数据并将图像数据输出到目的地设备，该设备包括缓冲器，缓冲器控制电路和帧写入控制器。 输入像素时钟不等于输出像素时钟。 帧写入控制器根据输入DE和输出DE生成写许可信号。 缓冲器控制电路根据输入DE和写允许信号产生写控制信号，并根据输出DE生成读控制信号。 缓冲器根据写控制信号和输入像素时钟从源装置接收图像数据，并根据读控制信号和输出像素时钟将图像数据输出到目的地装置。

公开(公告)号：US20080266454A1

公开(公告)日：2008-10-30

申请号：US12109868

申请日：2008-04-25

申请人： Tzuo-Bo Lin ,  Wen-Hsia Kung ,  Hsien-Chun Chang

发明人： Tzuo-Bo Lin ,  Wen-Hsia Kung ,  Hsien-Chun Chang

IPC分类号： H03L7/00 ,  H04N5/04

CPC分类号： H04N5/04 ,  H03L7/06

摘要： The invention discloses a sink device. The sink device comprises a buffering unit and a clock generating unit. The buffering unit receives a decoding data according to a symbol clock signal, reads the decoding data according to a pixel clock signal, and generates a water level value. The clock generating unit receives the symbol clock signal to generate the pixel clock signal and adjusts a rate of the pixel clock signal according to the water level value and/or a phase difference signal.

摘要翻译： 本发明公开了一种信宿设备。 宿设备包括缓冲单元和时钟发生单元。 缓冲单元根据符号时钟信号接收解码数据，根据像素时钟信号读取解码数据，并产生水位值。 时钟发生单元接收符号时钟信号以产生像素时钟信号，并根据水位值和/或相位差信号调整像素时钟信号的速率。

公开(公告)号：US20080211821A1

公开(公告)日：2008-09-04

申请号：US12010374

申请日：2008-01-24

申请人： Tzuo-Bo Lin ,  Wen-Hsia Kung

发明人： Tzuo-Bo Lin ,  Wen-Hsia Kung

IPC分类号： G09G5/00 ,  G06F3/033

CPC分类号： G09G5/006

摘要： A method for reducing output rate of video data for DisplayPort sink device is disclosed. By reducing the size of a blank area in a video frame, the invention reduces a pixel rate to become compatible with more types of back-end circuits having lower processing rates.

摘要翻译： 公开了一种用于降低DisplayPort宿设备的视频数据输出速率的方法。 通过减小视频帧中的空白区域的大小，本发明降低像素速率以与具有较低处理速率的更多类型的后端电路相兼容。

公开(公告)号：US08331460B2

公开(公告)日：2012-12-11

申请号：US12109868

申请日：2008-04-25

申请人： Tzuo-Bo Lin ,  Wen-Hsia Kung ,  Hsien-Chun Chang

发明人： Tzuo-Bo Lin ,  Wen-Hsia Kung ,  Hsien-Chun Chang

IPC分类号： H04N7/12 ,  H04N11/02 ,  H04N11/04

CPC分类号： H04N5/04 ,  H03L7/06

摘要： The invention discloses a sink device. The sink device comprises a buffering unit and a clock generating unit. The buffering unit receives a decoding data according to a symbol clock signal, reads the decoding data according to a pixel clock signal, and generates a water level value. The clock generating unit receives the symbol clock signal to generate the pixel clock signal and adjusts a rate of the pixel clock signal according to the water level value and/or a phase difference signal.

摘要翻译： 本发明公开了一种信宿设备。 宿设备包括缓冲单元和时钟发生单元。 缓冲单元根据符号时钟信号接收解码数据，根据像素时钟信号读取解码数据，并产生水位值。 时钟发生单元接收符号时钟信号以产生像素时钟信号，并根据水位值和/或相位差信号调整像素时钟信号的速率。

公开(公告)号：US08330761B2

公开(公告)日：2012-12-11

申请号：US12010374

申请日：2008-01-24

申请人： Tzuo-Bo Lin ,  Wen-Hsia Kung

发明人： Tzuo-Bo Lin ,  Wen-Hsia Kung

IPC分类号： G06F15/00

CPC分类号： G09G5/006

摘要： A method for reducing output rate of video data for DisplayPort sink device is disclosed. By reducing the size of a blank area in a video frame, the invention reduces a pixel rate to become compatible with more types of back-end circuits having lower processing rates.

摘要翻译： 公开了一种用于降低DisplayPort宿设备的视频数据输出速率的方法。 通过减小视频帧中的空白区域的大小，本发明降低像素速率以与具有较低处理速率的更多类型的后端电路相兼容。

公开(公告)号：US07945706B2

公开(公告)日：2011-05-17

申请号：US12128634

申请日：2008-05-29

申请人： An-Ming Lee ,  Tzu-Chien Tzeng ,  Yu-Pin Chou ,  Tzuo-Bo Lin

发明人： An-Ming Lee ,  Tzu-Chien Tzeng ,  Yu-Pin Chou ,  Tzuo-Bo Lin

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： H04N5/4401 ,  H04N5/46 ,  H04N5/765 ,  H04N21/42615 ,  H04N21/4305 ,  H04N21/436 ,  H04N21/4363

摘要： The invention provides a signal receiving circuit applied to multiple digital video/audio transmission interface standards. The signal receiving circuit includes at least an input interface for receiving an input signal, and at least an interface circuit. The input interface includes a set of shared input terminals, a set of first separate input terminals for receiving an input signal corresponding to a first transmission specification with the set of shared input terminals, and a set of second separate input terminals for receiving an input signal corresponding to a second transmission specification with the set of shared input terminals. The interface circuit includes a control circuit coupled to the input interface for supplying a control signal, and a processing module coupled to the input interface and the control circuit for processing the input signal according to the control signal to generate an output signal.

摘要翻译： 本发明提供一种应用于多个数字视频/音频传输接口标准的信号接收电路。 信号接收电路至少包括用于接收输入信号的输入接口和至少一个接口电路。 输入接口包括一组共享输入端子，一组第一分离输入端子，用于接收与该组共享输入端子对应的第一传输规格的输入信号，以及一组用于接收输入信号的第二单独输入端子 对应于具有该组共享输入端的第二传输规范。 接口电路包括耦合到用于提供控制信号的输入接口的控制电路，以及耦合到输入接口和控制电路的处理模块，用于根据控制信号处理输入信号以产生输出信号。

公开(公告)号：US08514206B2

公开(公告)日：2013-08-20

申请号：US12314601

申请日：2008-12-12

申请人： Yu-Pin Chou ,  Tzuo-Bo Lin ,  Ming-Syun Wu

发明人： Yu-Pin Chou ,  Tzuo-Bo Lin ,  Ming-Syun Wu

IPC分类号： G09G5/00

CPC分类号： G09G5/006 ,  G09G5/005 ,  G09G2370/12

摘要： A timing controller for a display processing device includes: a plurality of predetermined pins for receiving an image signal by a pin-share method, wherein the image signal is a first format image signal or a second format image signal; a detector coupled to the predetermined pins and for detecting at least one of the predetermined pins to determine whether the image signal is the first format image signal or the second format image signal and outputting a detection result; and a processor coupled to the detector and for processing the image signal according to the detection result to generate and output a timing control signal.

公开(公告)号：US20100014621A1

公开(公告)日：2010-01-21

申请号：US12501959

申请日：2009-07-13

申请人： Tzuo-Bo Lin ,  Bing-Juo Chuang ,  Yu-Pin Chou

发明人： Tzuo-Bo Lin ,  Bing-Juo Chuang ,  Yu-Pin Chou

IPC分类号： H04L7/00

CPC分类号： H04L7/10 ,  G09G5/006 ,  G09G5/008 ,  G09G2370/12 ,  H04L7/046 ,  H04L25/4908

摘要： A receiver includes; a recovery circuit for receiving an input signal, and generating a data signal and a recovery clock; a processing circuit for processing the data signal to generate a processed signal; and a synchronization determining circuit for determining a synchronization state of the recovery clock according to the processed signal and a first reference value. The data signal includes a synchronous pattern, and the first reference value corresponds to at least a portion of a value in the synchronous pattern processed by the processing circuit. A method of the receiver is also disclosed.

摘要翻译： 接收机包括 恢复电路，用于接收输入信号，并产生数据信号和恢复时钟; 处理电路，用于处理数据信号以产生处理的信号; 以及同步确定电路，用于根据处理的信号和第一参考值确定恢复时钟的同步状态。 数据信号包括同步模式，第一参考值对应于由处理电路处理的同步模式中的值的至少一部分。 还公开了接收机的方法。