公开(公告)号：US20130113020A1

公开(公告)日：2013-05-09

申请号：US13613236

申请日：2012-09-13

申请人： Donghua Liu ,  Wenting Duan ,  Wensheng Qian ,  Jun Hu ,  Jing Shi

发明人： Donghua Liu ,  Wenting Duan ,  Wensheng Qian ,  Jun Hu ,  Jing Shi

IPC分类号： H01L29/737 ,  H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7371

摘要： A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed.

摘要翻译： 公开了一种SiGe HBT，其包括：硅衬底; 形成在硅衬底中的浅沟槽场氧化物; 形成在每个浅沟槽场氧化物的底部的伪掩埋层; 形成在所述硅衬底的表面下方的集电极区域，所述集电极区域夹在所述浅沟槽场氧化物之间和所述伪埋层之间; 形成在每个浅沟槽场氧化物上方的多晶硅栅极，其厚度大于150nm; 多晶硅栅极和集电极区域上的基极区域; 发射极区隔离氧化物; 并且发射极区域上的发射极区域隔离氧化物和基极区域的一部分。 多晶硅栅极通过CMOS工艺中的MOSFET的栅极多晶硅工艺形成。 还公开了制造SiGe HBT的方法。

公开(公告)号：US08420475B2

公开(公告)日：2013-04-16

申请号：US12975545

申请日：2010-12-22

申请人： Tzuyin Chiu ,  TungYuan Chu ,  Wensheng Qian ,  YungChieh Fan ,  Donghua Liu ,  Jun Hu

发明人： Tzuyin Chiu ,  TungYuan Chu ,  Wensheng Qian ,  YungChieh Fan ,  Donghua Liu ,  Jun Hu

IPC分类号： H01L21/8238

CPC分类号： H01L29/732 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7371

摘要： This invention published a parasitic vertical PNP bipolar transistor in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process; the bipolar transistor comprises a collector, a base and an emitter. Collector is formed by active region with p-type ion implanting layer. It connects a p-type buried layer which formed in the bottom region of STI (Shallow Trench Isolation). The collector terminal connection is through the p-type buried layer and the adjacent active region. The base is formed by active region with n type ion implanting which is on the collector. Its connection is through the original p-type epitaxy layer after converting to n-type. The emitter is formed by the p-type epitaxy layer on the base region with heavy p-type doped. This invention also comprises the fabrication method of this parasitic vertical PNP bipolar in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process. And this PNP bipolar transistor can be used as the IO (Input/Output) device in high speed, high current and power gain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) circuits. It also provides a device option with low cost.

摘要翻译： 本发明公开了BiCMOS（双极互补金属氧化物半导体）工艺中的寄生垂直PNP双极晶体管; 双极晶体管包括集电极，基极和发射极。 集电极由具有p型离子注入层的有源区形成。 它连接形成在STI底部区域（浅沟槽隔离）的p型掩埋层。 集电极端子连接通过p型掩埋层和相邻的有源区。 基极由在集电极上的n型离子注入的有源区形成。 其连接是通过原始的p型外延层转换为n型。 发射极由重p型掺杂的基极区上的p型外延层形成。 本发明还包括BiCMOS（双极互补金属氧化物半导体）工艺中该寄生垂直PNP双极的制造方法。 而这种PNP双极晶体管可以用作高速，大电流和功率增益BiCMOS（双极互补金属氧化物半导体）电路中的IO（输入/输出）器件。 它还提供低成本的设备选项。

公开(公告)号：US20110156202A1

公开(公告)日：2011-06-30

申请号：US12978552

申请日：2010-12-25

申请人： Tzuyin CHIU ,  TungYuan Chu ,  Wensheng Qian ,  YungChieh Fan ,  Donghua Liu ,  Jun Hu

发明人： Tzuyin CHIU ,  TungYuan Chu ,  Wensheng Qian ,  YungChieh Fan ,  Donghua Liu ,  Jun Hu

IPC分类号： H01L29/70

CPC分类号： H01L29/0821 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7371 ,  H01L2924/0002 ,  H01L2924/00

摘要： A parasitic vertical PNP device in one type of BiCMOS process with shallow trench isolation (STI) comprises a collector formed by a p type impurity ion implantation layer inside active area, the bottom of collector connects to a p type buried layer, the p type pseudo buried layer is formed in bottom of shallow trench at both sides of collector active region through ion implantation, deep contacts through field oxide to connect pseudo buried layers and to pick up the collector; a base, formed by n type impurity ion implantation layer which sits on top of above stated collector; an emitter, a p type epitaxy layer lies above base and is connected out directly by a metal contact. Part of the p type epitaxy layer is converted into n type, which serves as connection path of base. Present invented PNP can be used as output device of BiCMOS high frequency circuit. It has a small device area and conduction resistance.

摘要翻译： 具有浅沟槽隔离（STI）的一种类型的BiCMOS工艺中的寄生垂直PNP器件包括由有源区内的ap型杂质离子注入层形成的集电极，集电极的底部连接到ap型掩埋层，p型伪掩埋层 通过离子注入形成在集电极有源区两侧的浅沟底部，通过场氧化物深接触连接伪埋层并拾取收集器; 由位于上述收集器顶部的n型杂质离子注入层形成的基底; 发射极，p型外延层位于基底之上，并通过金属接触直接连接。 p型外延层的一部分被转换为n型，其用作基极的连接路径。 本发明的PNP可用作BiCMOS高频电路的输出装置。 它具有小的器件面积和导通电阻。

公开(公告)号：US08637959B2

公开(公告)日：2014-01-28

申请号：US13220485

申请日：2011-08-29

申请人： Wensheng Qian ,  Donghua Liu ,  Jun Hu

发明人： Wensheng Qian ,  Donghua Liu ,  Jun Hu

IPC分类号： H01L21/02

CPC分类号： H01L29/7371 ,  H01L21/76224 ,  H01L21/8249 ,  H01L29/0817 ,  H01L29/161 ,  H01L29/41708 ,  H01L29/66242

摘要： The invention discloses a vertical parasitic PNP transistor in a BiCMOS process and manufacturing method of the same, wherein an active region is isolated by STIs. The transistor includes a collector region, a base region, an emitter region, pseudo buried layers, and N-type polysilicon. The pseudo buried layers, formed at the bottom of the STIs located on both sides of the collector region, extend laterally into the active region and contact with the collector region, whose electrodes are picked up through making deep-hole contacts in the STIs. The N-type polysilicon is formed on the base region and contacts with it, whose electrodes are picked up through making metal contacts on the N-type polysilicon. The transistors can be used as output devices in high-speed and high-gain circuits, efficiently reducing the transistors area, diminishing the collector resistance, and improving the transistors performance. The method can reduce the cost without additional technological conditions.

摘要翻译： 本发明公开了一种BiCMOS工艺中的垂直寄生PNP晶体及其制造方法，其中有源区由STI分离。 晶体管包括集电极区域，基极区域，发射极区域，伪掩埋层和N型多晶硅。 形成在位于集电区域两侧的STI的底部的伪掩埋层横向延伸到有源区并与集电区接触，该集电极区通过在STI中形成深孔接触来拾取电极。 N型多晶硅形成在基极区上并与其接触，其电极通过在N型多晶硅上形成金属接触来拾取。 晶体管可以用作高速和高增益电路中的输出器件，有效降低晶体管面积，减小集电极电阻，并提高晶体管的性能。 该方法可以降低成本而不需要额外的技术条件。

公开(公告)号：US08598678B2

公开(公告)日：2013-12-03

申请号：US12963242

申请日：2010-12-08

申请人： Wensheng Qian ,  Jun Hu ,  Donghua Liu

发明人： Wensheng Qian ,  Jun Hu ,  Donghua Liu

IPC分类号： H01L29/732 ,  H01L21/8228

CPC分类号： H01L29/732 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66272

摘要： A parasitic vertical PNP bipolar transistor in BiCMOS process comprises a collector, a base and an emitter. The collector is formed by active region with p-type ion implanting layer (P type well in NMOS). It connects a P-type conductive region, which formed in the bottom region of shallow trench isolation (STI). The collector terminal connection is through the P-type buried layer and the adjacent active region. The base is formed by N type ion implanting layer above the collector which shares a N-type lightly doped drain (NLDD) implanting of NMOS. Its connection is through the N-type poly on the base region. The emitter is formed by the P-type epitaxy layer on the base region with heavy p-type doped, and connected by the extrinsic base region of NPN bipolar transistor device. This invention also includes the fabrication method of this parasitic vertical PNP bipolar transistor in BiCMOS process. And this PNP bipolar transistor can be used as the I/O (input/output) device in high speed, high current and power gain BiCMOS circuits. It also provides a device option with low cost.

摘要翻译： BiCMOS工艺中的寄生垂直PNP双极晶体管包括集电极，基极和发射极。 集电极由具有p型离子注入层（P型阱在NMOS中）的有源区形成。 它连接形成在浅沟槽隔离（STI）的底部区域中的P型导电区域。 集电极端子连接通过P型掩埋层和相邻的有源区。 基极由收集器上方的N型离子注入层形成，其共享NMOS的N型轻掺杂漏极（NLDD）注入。 其连接是通过基底区域上的N型聚合物。 发射极由P型掺杂的P型外延层构成，并由NPN双极晶体管器件的非本征基极区连接。 本发明还包括在BiCMOS工艺中该寄生垂直PNP双极晶体管的制造方法。 该PNP双极晶体管可用作高速，大电流和功率增益BiCMOS电路中的I / O（输入/输出）器件。 它还提供低成本的设备选项。

公开(公告)号：US08674480B2

公开(公告)日：2014-03-18

申请号：US12966078

申请日：2010-12-13

申请人： Tzuyin Chiu ,  TungYuan Chu ,  Wensheng Qian ,  YungChieh Fan ,  Jun Hu ,  Donghua Liu ,  Yukun Lv

发明人： Tzuyin Chiu ,  TungYuan Chu ,  Wensheng Qian ,  YungChieh Fan ,  Jun Hu ,  Donghua Liu ,  Yukun Lv

IPC分类号： H01L29/66

CPC分类号： H01L21/76232 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0657 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7322 ,  H01L29/7378

摘要： A high voltage bipolar transistor with shallow trench isolation (STI) comprises the areas of a collector formed by implanting first electric type impurities into active area and connected with pseudo buried layers at two sides; Pseudo buried layers which are formed by implanting high dose first type impurity through the bottoms of STI at two sides if active area, and do not touch directly; deep contact through field oxide to contact pseudo buried layers and pick up the collectors; a base deposited on the collector by epitaxial growth and in-situ doped by second electric type impurity, in which the intrinsic base touches local collector and extrinsic base is used for base pick-up; a emitter which is a polysilicon layer deposited on the intrinsic base and doped with first electric type impurities. This invention makes the depletion region of collector/base junction from 1D (vertical) distribution to 2D (vertical and lateral) distribution. The bipolar transistor's breakdown voltages are increased by only enlarge active critical dimension (CD). This is low-cost process.

摘要翻译： 具有浅沟槽隔离（STI）的高电压双极晶体管包括通过将第一电型杂质注入有源区并且在两侧与伪掩埋层连接而形成的集电极的区域; 伪埋层是通过在两侧的STI两侧植入高剂量第一类杂质而形成的，如果有活动区域，并且不直接接触; 通过场氧化物深接触接触伪埋层并拾取集电器; 通过外延生长沉积在集电体上并通过第二电型杂质原位掺杂的基极，其中本征基极接触局部集电极和外部基极用于基极拾取; 作为沉积在本征基底上并掺杂有第一电型杂质的多晶硅层的发射极。 本发明使集电极/基极结的耗尽区从1D（垂直）分布到2D（垂直和横向）分布。 双极晶体管的击穿电压仅通过增加主动临界尺寸（CD）来增加。 这是低成本的过程。

公开(公告)号：US20130113078A1

公开(公告)日：2013-05-09

申请号：US13613209

申请日：2012-09-13

申请人： Donghua Liu ,  Wenting Duan ,  Wensheng Qian ,  Jun Hu ,  Jing Shi

发明人： Donghua Liu ,  Wenting Duan ,  Wensheng Qian ,  Jun Hu ,  Jing Shi

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L29/94 ,  H01L29/66181

摘要： A PIS capacitor in a SiGe HBT process is disclosed, wherein the PIS capacitor includes: a silicon substrate; a P-well and shallow trench isolations formed in the silicon substrate; a P-type heavily doped region formed in an upper portion of the P-well; an oxide layer and a SiGe epitaxial layer formed above the P-type heavily doped region; spacers formed on sidewalls of the oxide layer and the SiGe epitaxial layer; and contact holes for picking up the P-well and the SiGe epitaxial layer and connecting each of the P-well and the SiGe epitaxial layer to a metal wire. A method of manufacturing the PIS capacitor is also disclosed. The PIS capacitor of the present invention is manufactured by using SiGe HBT process, thus providing one more device option for the SiGe HBT process.

摘要翻译： 公开了SiGe HBT工艺中的PIS电容器，其中PIS电容器包括：硅衬底; 在硅衬底中形成的P阱和浅沟槽隔离; 形成在P阱的上部的P型重掺杂区域; 在P型重掺杂区域上形成氧化物层和SiGe外延层; 在氧化物层和SiGe外延层的侧壁上形成间隔物; 以及用于拾取P阱和SiGe外延层的接触孔，并将P阱和SiGe外延层中的每一个连接到金属线。 还公开了一种制造PIS电容器的方法。 通过使用SiGe HBT工艺制造本发明的PIS电容器，从而为SiGe HBT工艺提供了一种更多的器件选择。

公开(公告)号：US20110156143A1

公开(公告)日：2011-06-30

申请号：US12975545

申请日：2010-12-22

申请人： Tzuyin CHIU ,  TungYuan Chu ,  Wensheng Qian ,  YungChieh Fan ,  Donghua Liu ,  Jun Hu

发明人： Tzuyin CHIU ,  TungYuan Chu ,  Wensheng Qian ,  YungChieh Fan ,  Donghua Liu ,  Jun Hu

IPC分类号： H01L27/07 ,  H01L21/8249

CPC分类号： H01L29/732 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7371

摘要： This invention published a parasitic vertical PNP bipolar transistor in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process; the bipolar transistor comprises a collector, a base and an emitter. Collector is formed by active region with p-type ion implanting layer. It connects a p-type buried layer which formed in the bottom region of STI (Shallow Trench Isolation). The collector terminal connection is through the p-type buried layer and the adjacent active region. The base is formed by active region with n type ion implanting which is on the collector. Its connection is through the original p-type epitaxy layer after converting to n-type. The emitter is formed by the p-type epitaxy layer on the base region with heavy p-type doped. This invention also comprises the fabrication method of this parasitic vertical PNP bipolar in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process. And this PNP bipolar transistor can be used as the IO (Input/Output) device in high speed, high current and power gain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) circuits. It also provides a device option with low cost.

摘要翻译： 本发明公开了BiCMOS（双极互补金属氧化物半导体）工艺中的寄生垂直PNP双极晶体管; 双极晶体管包括集电极，基极和发射极。 集电极由具有p型离子注入层的有源区形成。 它连接形成在STI底部区域（浅沟槽隔离）的p型掩埋层。 集电极端子连接通过p型掩埋层和相邻的有源区。 基极由在集电极上的n型离子注入的有源区形成。 其连接是通过原始的p型外延层转换为n型。 发射极由重p型掺杂的基极区上的p型外延层形成。 本发明还包括BiCMOS（双极互补金属氧化物半导体）工艺中该寄生垂直PNP双极的制造方法。 而这种PNP双极晶体管可以用作高速，大电流和功率增益BiCMOS（双极互补金属氧化物半导体）电路中的IO（输入/输出）器件。 它还提供低成本的设备选项。

公开(公告)号：US20110140233A1

公开(公告)日：2011-06-16

申请号：US12963242

申请日：2010-12-08

申请人： Wensheng QIAN ,  Jun Hu ,  Donghua Liu

发明人： Wensheng QIAN ,  Jun Hu ,  Donghua Liu

IPC分类号： H01L29/73 ,  H01L21/8228

CPC分类号： H01L29/732 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66272

摘要： A parasitic vertical PNP bipolar transistor in BiCMOS process comprises a collector, a base and an emitter. The collector is formed by active region with p-type ion implanting layer (P type well in NMOS). It connects a P-type conductive region, which formed in the bottom region of shallow trench isolation (STI). The collector terminal connection is through the P-type buried layer and the adjacent active region. The base is formed by N type ion implanting layer above the collector which shares a N-type lightly doped drain (NLDD) implanting of NMOS. Its connection is through the N-type poly on the base region. The emitter is formed by the P-type epitaxy layer on the base region with heavy p-type doped, and connected by the extrinsic base region of NPN bipolar transistor device. This invention also includes the fabrication method of this parasitic vertical PNP bipolar transistor in BiCMOS process. And this PNP bipolar transistor can be used as the I/O (input/output) device in high speed, high current and power gain BiCMOS circuits. It also provides a device option with low cost.

摘要翻译： BiCMOS工艺中的寄生垂直PNP双极晶体管包括集电极，基极和发射极。 集电极由具有p型离子注入层（P型阱在NMOS中）的有源区形成。 它连接形成在浅沟槽隔离（STI）的底部区域中的P型导电区域。 集电极端子连接通过P型掩埋层和相邻的有源区。 基极由收集器上方的N型离子注入层形成，其共享NMOS的N型轻掺杂漏极（NLDD）注入。 其连接是通过基底区域上的N型聚合物。 发射极由P型掺杂的P型外延层构成，并由NPN双极晶体管器件的非本征基极区连接。 本发明还包括在BiCMOS工艺中该寄生垂直PNP双极晶体管的制造方法。 该PNP双极晶体管可用作高速，大电流和功率增益BiCMOS电路中的I / O（输入/输出）器件。 它还提供低成本的设备选项。

公开(公告)号：US09012279B2

公开(公告)日：2015-04-21

申请号：US13613236

申请日：2012-09-13

申请人： Donghua Liu ,  Wenting Duan ,  Wensheng Qian ,  Jun Hu ,  Jing Shi

发明人： Donghua Liu ,  Wenting Duan ,  Wensheng Qian ,  Jun Hu ,  Jing Shi

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/737 ,  H01L29/08

CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7371

摘要： A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed.

摘要翻译： 公开了一种SiGe HBT，其包括：硅衬底; 形成在硅衬底中的浅沟槽场氧化物; 形成在每个浅沟槽场氧化物的底部的伪掩埋层; 形成在所述硅衬底的表面下方的集电极区域，所述集电极区域夹在所述浅沟槽场氧化物之间和所述伪埋层之间; 形成在每个浅沟槽场氧化物上方的多晶硅栅极，其厚度大于150nm; 多晶硅栅极和集电极区域上的基极区域; 发射极区隔离氧化物; 并且发射极区域上的发射极区域隔离氧化物和基极区域的一部分。 多晶硅栅极通过CMOS工艺中的MOSFET的栅极多晶硅工艺形成。 还公开了制造SiGe HBT的方法。