利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

41 records (took 0.016 seconds)

    Adaptive Use of Multiple Channels in a Storage Device
    1.
    发明申请
    Adaptive Use of Multiple Channels in a Storage Device 有权

    公开(公告)号：US20250028462A1

    公开(公告)日：2025-01-23

    申请号：US18353857

    申请日：2023-07-17

    Applicant: Western Digital Technologies, Inc.

    Inventor： Shay BENISTY ,  Ariel NAVON ,  Alexander BAZARSKY ,  Judah Gamliel HAHN

    IPC: G06F3/06

    Abstract: More efficient memory device usage is possible by altering the memory device management. For example, when the full storage capacity of the memory device will not be used, certain portions of the memory device can be shut off and then turned on when the storage capacity is needed. When less capacity is needed, data can be consolidated and certain portions of the memory device can be shut off. Additionally, rather than operating in multilevel cell (MLC) memory, the memory device can start in single level cell (SLC) memory and transition to MLC memory over time. If there is a determination that less memory is needed, the memory device can transition from MLC memory to SLC memory. In so doing, the storage capacity of the memory device is more appropriately utilized.

    Mitigating DBI Bit Flip Induced Errors
    2.
    发明公开
    Mitigating DBI Bit Flip Induced Errors 审中-公开

    公开(公告)号：US20230208446A1

    公开(公告)日：2023-06-29

    申请号：US17646378

    申请日：2021-12-29

    Applicant: Western Digital Technologies, Inc.

    Inventor： Shay BENISTY ,  Judah Gamliel HAHN ,  Ariel NAVON

    IPC: H03M13/45

    CPC classification number: H03M13/45

    Abstract: The present disclosure generally relates to improving data transfer in a data storage device. In double data rate (DDR) systems that include a data bus inversion (DBI) functionality, bit flip events can be more prevalent. To mitigate the effect of enhanced erroneous bit flip rate related to DBI bit flip events, the DBI bit can stay static for a predetermined number of consecutive clock cycles, the error correction module can be informed of reduced reliability due to active DBI bit events, the DBI bit can be set to 0, or combinations thereof. Setting the DBI bit to 0 effectively cancels DBI functionality. Informing the error correction module permits a more robust error correction to occur. Forcing the DBI bit to remain static reduces the probability of an unrecognized bit flip event of a full byte. In so doing, data transfer reliability is improved when using DBI functionality.

    Enhanced D3-Cold And Faster Recovery
    3.
    发明申请
    Enhanced D3-Cold And Faster Recovery 有权

    公开(公告)号：US20220327244A1

    公开(公告)日：2022-10-13

    申请号：US17224732

    申请日：2021-04-07

    Applicant: Western Digital Technologies, Inc.

    Inventor： Shay BENISTY ,  Judah Gamliel HAHN ,  Ariel NAVON

    IPC: G06F21/78 ,  G06F21/57 ,  G06F21/60 ,  G06F1/3234

    Abstract: A data storage device includes a memory device, an always on (AON) application specific integrated circuit (ASIC), and a controller coupled to the memory device and the AON ASIC. When the data storage device enters a low power state, the controller generates and stores security data associated with context data in a power management integrated circuit (PMIC). The context data is stored in both the memory device and a host memory buffer (HMB). A location of the context data in the HMB is stored in the PMIC with the security data. When the data storage device exits the low power state, the address stored in the PMIC is utilized to retrieve the context data from the HMB. The retrieved context data is verified against the security data by the controller.

    Prediction-Based Selective Flushing Of Data To Memory
    4.
    发明申请
    Prediction-Based Selective Flushing Of Data To Memory 有权

    公开(公告)号：US20220107893A1

    公开(公告)日：2022-04-07

    申请号：US17211592

    申请日：2021-03-24

    Applicant: Western Digital Technologies, Inc.

    Inventor： Shay BENISTY ,  Ariel NAVON

    IPC: G06F12/0804

    Abstract: The present disclosure generally relates to improving write cache utilization by recommending a time to initiate a data flush operation or predicting when a new write command will arrive. The recommending can be based upon considerations such as a hard time limit for data caching, rewarding for filling the cache, and penalizing for holding data for too long. The predicting can be based on tracking write command arrivals and then, based upon the tracking, predicting an estimated arrival time for the next write command. Based upon the recommendation or predicting, the write cache can be flushed or the data can remain in the write cache to thus more efficiently utilize the write cache without violating a hard stop time limit.

    SSD Content Preloading Via Broadcasting System
    6.
    发明申请
    SSD Content Preloading Via Broadcasting System 有权

    公开(公告)号：US20240419331A1

    公开(公告)日：2024-12-19

    申请号：US18218874

    申请日：2023-07-06

    Applicant: Western Digital Technologies, Inc.

    Inventor： Julian VLAIKO ,  Judah Gamliel HAHN ,  Shay BENISTY ,  Ariel NAVON ,  Alexander BAZARSKY ,  Aki BLEYER

    IPC: G06F3/06

    Abstract: In a storage system having a plurality of solid state drives (SSDs), the performance of propagating data from a primary device to each secondary device may be improved using a dedicated high speed data channel in which data and commands associated with the data is sent from an upstream SSD to a downstream SSD. The data is also sent to the downstream SSD after a minimum amount of data has been programmed to the upstream SSD. The downstream SSD begins programming the data to its own memory device after receiving the data. The programming of data to each SSD of the storage system may be in parallel and at least partially concurrent with each other. Data, commands, and control messages may be sent an upstream SSD via a serial bus or a universal asynchronous receiver-transmitter channel, such that the downstream data paths and the upstream data paths are distinct.

    ADAPTIVE TUNING OF MEMORY DEVICE CLOCK RATES BASED ON DYNAMIC PARAMETERS
    8.
    发明公开
    ADAPTIVE TUNING OF MEMORY DEVICE CLOCK RATES BASED ON DYNAMIC PARAMETERS 审中-公开

    公开(公告)号：US20240078026A1

    公开(公告)日：2024-03-07

    申请号：US17939186

    申请日：2022-09-07

    Applicant: Western Digital Technologies, Inc.

    Inventor： Shay BENISTY ,  Ariel NAVON ,  Alexander BAZARSKY ,  David AVRAHAM

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0673

    Abstract: The present disclosure generally relates to improving adaptive tuning of different clock rates of a memory device. Rather than clock rates only being determined off of one parameter such as workload, the clock rates now will be determined using multiple parameters. The tuning may be based on system parameters to allow the system to withstand challenges that arise during the operation. The clock frequency table is maintained in the device controller. The table holds the clock frequency of each component. The disclosure proposes modifying the table according to different system environment parameters to maintain performance or reduce power consumption. Adaptive tuning allows a more flexible system design that can adapt according to the current system status. Adaptive tuning also reduces peak power consumption, improves performance, and better quality of service (QoS) compatibility characteristics.

    NVMe Boot Partition Error Correction Code Enhancement
    9.
    发明公开
    NVMe Boot Partition Error Correction Code Enhancement 审中-公开

    公开(公告)号：US20240054047A1

    公开(公告)日：2024-02-15

    申请号：US17887687

    申请日：2022-08-15

    Applicant: Western Digital Technologies, Inc.

    Inventor： Alexander BAZARSKY ,  Judah Gamliel HAHN ,  Shay BENISTY ,  Ariel NAVON

    IPC: G06F11/10 ,  G06F9/4401

    CPC classification number: G06F11/1048 ,  G06F9/441

    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to compare a first copy of a boot partition to a second copy of the boot partition. The first copy of the boot partition and the second copy of the boot partition each comprises a same number of a plurality of boot chunks. The boot partition corresponds to data of a boot operation of a host device. The controller is further configured to mark one or more of the compared boot chunks that equals or exceeds a similarity threshold and update a reliability index based on the marking. Based on the marking and the reliability index, the controller may increase or decrease an amount of error correction needed for the boot data.

Patent Agency Ranking