公开(公告)号：US06974983B1

公开(公告)日：2005-12-13

申请号：US10768660

申请日：2004-02-02

Applicant: Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/062

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A semiconductor device includes an N-channel device and a P-channel device. The N-channel device includes a first source region, a first drain region, a first fin structure, and a gate. The P-channel device includes a second source region, a second drain region, a second fin structure, and the gate. The second source region, the second drain region, and the second fin structure are separated from the first source region, the first drain region, and the first fin structure by a channel stop layer.

Abstract translation: 半导体器件包括N沟道器件和P沟道器件。 N沟道器件包括第一源极区，第一漏极区，第一鳍结构和栅极。 P沟道器件包括第二源极区，第二漏极区，第二鳍结构和栅极。 第二源极区域，第二漏极区域和第二鳍状结构通过沟道阻挡层与第一源极区域，第一漏极区域和第一鳍片结构分离。

公开(公告)号：US06914277B1

公开(公告)日：2005-07-05

申请号：US10674400

申请日：2003-10-01

Applicant: Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A semiconductor device includes an N-channel device and a P-channel device. The N-channel device includes a first source region, a first drain region, a first fin structure, and a gate. The P-channel device includes a second source region, a second drain region, a second fin structure, and the gate. The second source region, the second drain region, and the second fin structure are separated from the first source region, the first drain region, and the first fin structure by an insulating layer.

Abstract translation: 半导体器件包括N沟道器件和P沟道器件。 N沟道器件包括第一源极区，第一漏极区，第一鳍结构和栅极。 P沟道器件包括第二源极区，第二漏极区，第二鳍结构和栅极。 第二源极区域，第二漏极区域和第二鳍状结构通过绝缘层与第一源极区域，第一漏极区域和第一鳍片结构分离。

公开(公告)号：US07298007B1

公开(公告)日：2007-11-20

申请号：US11171399

申请日：2005-07-01

Applicant: Wiley Eugene Hill ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Bin Yu

IPC: H01L29/76

CPC classification number: H01L27/1108 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1211 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903 ,  Y10S438/944

Abstract: A memory device includes multiple fins formed adjacent to one another, a source region, a drain region, a gate, a wordline, and a bitline contact. At least one of the multiple fins is doped with a first type of impurities and at least one other one of the fins is doped with a second type of impurities. The source region is formed at one end of each of the fins and the drain region is formed at an opposite end of each of the fins. The gate is formed over two of the multiple fins, the wordline is formed over each of the multiple fins, and a bitline contact is formed adjacent at least one of the multiple fins.

Abstract translation: 存储器件包括彼此相邻形成的多个鳍，源极区，漏极区，栅极，字线和位线接触。 多个翅片中的至少一个被掺杂有第一类型的杂质，并且至少另外一个翅片掺杂有第二类型的杂质。 源区域形成在每个散热片的一端，并且漏极区域形成在每个散热片的相对端。 栅极形成在多个散热片的两个之上，字线形成在多个散热片的每一个上，并且与多个散热片中的至少一个相邻地形成有位线接触。

公开(公告)号：US07064022B1

公开(公告)日：2006-06-20

申请号：US10728844

申请日：2003-12-08

Applicant: Wiley Eugene Hill ,  Ming-Ren Lin ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Ming-Ren Lin ,  Bin Yu

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/7854 ,  H01L21/26586 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/66795

Abstract: A method forms a semiconductor device from a device that includes a first source region, a first drain region, and a first fin structure that are separated from a second source region, a second drain region, and a second fin structure by an insulating layer. The method may include forming a dielectric layer over the device and removing portions of the dielectric layer to create covered portions and bare portions. The method may also include depositing a gate material over the covered portions and bare portions, doping the first fin structure, the first source region, and the first drain region with a first material, and doping the second fin structure, the second source region, and the second drain region with a second material. The method may further include removing a portion of the gate material over at least one covered portion to form the semiconductor device.

Abstract translation: 一种方法从包括通过绝缘层与第二源极区域，第二漏极区域和第二鳍状结构分离的第一源极区域，第一漏极区域和第一鳍状物结构的器件形成半导体器件。 该方法可以包括在器件上形成电介质层并去除介电层的部分以产生被覆盖部分和裸露部分。 该方法还可以包括在覆盖部分和裸露部分上沉积栅极材料，用第一材料掺杂第一鳍片结构，第一源极区域和第一漏极区域，并掺杂第二鳍片结构，第二源极区域， 和具有第二材料的第二漏区。 该方法还可以包括在至少一个被覆部分上去除栅极材料的一部分以形成半导体器件。

公开(公告)号：US06933558B2

公开(公告)日：2005-08-23

申请号：US10726508

申请日：2003-12-04

Applicant: Wiley Eugene Hill ,  Haihong Wang ,  Yider Wu ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Haihong Wang ,  Yider Wu ,  Bin Yu

IPC: G11C16/04 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/785

Abstract: A memory device includes a conductive structure, a number of dielectric layers and a control gate. The dielectric layers are formed around the conductive structure and the control gate is formed over the dielectric layers. A portion of the conductive structure functions as a drain region for the memory device and at least one of the dielectric layers functions as a charge storage structure for the memory device. The dielectric layers may include oxide-nitride-oxide layers.

Abstract translation: 存储器件包括导电结构，多个电介质层和控制栅极。 电介质层形成在导电结构周围，并且控制栅极形成在电介质层上。 导电结构的一部分用作存储器件的漏极区，并且至少一个介电层用作存储器件的电荷存储结构。 电介质层可以包括氧化物 - 氮化物 - 氧化物层。

公开(公告)号：US06787406B1

公开(公告)日：2004-09-07

申请号：US10638334

申请日：2003-08-12

Applicant: Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L2184

CPC classification number: H01L29/785 ,  H01L21/26586 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/66803 ,  Y10S438/944

Abstract: A method facilitates the doping of fins of a semiconductor device that includes a substrate. The method includes forming fin structures on the substrate, where each of the fin structures includes a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first one of the fins with n-type impurities and performing a second tilt angle implant process to dope a second one of the fins with p-type impurities.

Abstract translation: 一种方法有助于掺杂包括衬底的半导体器件的散热片。 该方法包括在基板上形成翅片结构，其中每个翅片结构都包括形成在翅片上的盖。 该方法还包括执行第一倾斜角度注入工艺以用n型杂质掺杂第一个翅片，并执行第二倾斜角度注入工艺，以使p型杂质掺杂第二个翅片。

公开(公告)号：US07297581B1

公开(公告)日：2007-11-20

申请号：US11130161

申请日：2005-05-17

Applicant: Wiley Eugene Hill ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Bin Yu

IPC: H01L21/338

CPC classification number: H01L27/1108 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1211 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903 ,  Y10S438/944

Abstract: A method of doping fins of a semiconductor device that includes a substrate includes forming multiple fin structures on the substrate, each of the fin structures including a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first pair of the multiple fin structures with n-type impurities and performing a second tilt angle implant process to dope a second pair of the multiple fin structures with p-type impurities.

Abstract translation: 掺杂包括衬底的半导体器件的散热片的方法包括在衬底上形成多个翅片结构，每个翅片结构包括形成在翅片上的盖。 该方法还包括执行第一倾斜角度注入过程以用n型杂质掺杂第一对多鳍片结构，并执行第二倾斜角度注入工艺以将第二对多鳍片结构与p型杂质掺杂。

公开(公告)号：US06924561B1

公开(公告)日：2005-08-02

申请号：US10728910

申请日：2003-12-08

Applicant: Wiley Eugene Hill ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Bin Yu

IPC: H01L21/336 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1108 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1211 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903 ,  Y10S438/944

Abstract: A memory device includes multiple fins formed adjacent to one another, a source region, a drain region, a gate, a wordline, and a bitline contact. At least one of the multiple fins is doped with a first type of impurities and at least one other one of the fins is doped with a second type of impurities. The source region is formed at one end of each of the fins and the drain region is formed at an opposite end of each of the fins. The gate is formed over two of the multiple fins, the wordline is formed over each of the multiple fins, and a bitline contact is formed adjacent at least one of the multiple fins.

Abstract translation: 存储器件包括彼此相邻形成的多个鳍，源极区，漏极区，栅极，字线和位线接触。 多个翅片中的至少一个被掺杂有第一类型的杂质，并且至少另外一个翅片掺杂有第二类型的杂质。 源区域形成在每个散热片的一端，并且漏极区域形成在每个散热片的相对端。 栅极形成在多个散热片的两个之上，字线形成在多个散热片的每一个上，并且与多个散热片中的至少一个相邻地形成有位线接触。

公开(公告)号：US20150286441A1

公开(公告)日：2015-10-08

申请号：US14746582

申请日：2015-06-22

Applicant: Aswani Kumar Raveendran Nair ,  Sergiy Pereshyvaylo ,  Bin Yu ,  Sudheendra Vasudeva Murthy

Inventor： Aswani Kumar Raveendran Nair ,  Sergiy Pereshyvaylo ,  Bin Yu ,  Sudheendra Vasudeva Murthy

IPC: G06F3/06

CPC classification number: H04L41/0659 ,  G06F11/006 ,  G06F11/0709 ,  G06F11/0727 ,  G06F11/0793 ,  G06F11/1423 ,  G06F17/30194 ,  H04L67/06 ,  H04L67/1097

Abstract: A method and a system to provide daisy chain distribution in data centers are provided. A node identification module identifies three or more data nodes of a plurality of data nodes. The identification of three or more data nodes indicates that the respective data nodes are to receive a copy of a data file. A connection creation module to, using one or more processors, create communication connections between the three or more data nodes. The communication connections form a daisy chain beginning at a seeder data node of the three or more data nodes and ending at a terminal data node of the three or more data nodes.

Abstract translation: 提供了一种在数据中心提供菊花链分发的方法和系统。 节点识别模块识别多个数据节点中的三个或多个数据节点。 三个或更多个数据节点的标识指示相应的数据节点要接收数据文件的副本。 连接创建模块，用于使用一个或多个处理器在三个或更多个数据节点之间建立通信连接。 通信连接形成从三个或更多个数据节点的播种器数据节点开始并且结束于三个或更多个数据节点的终端数据节点的菊花链。

公开(公告)号：US09143297B2

公开(公告)日：2015-09-22

申请号：US13977907

申请日：2011-07-21

Applicant: Chunli Liang ,  Bo Dai ,  Bin Yu ,  Weiwei Yang ,  Yuqiang Zhang

Inventor： Chunli Liang ,  Bo Dai ,  Bin Yu ,  Weiwei Yang ,  Yuqiang Zhang

IPC: H04W4/00 ,  H04L5/00

CPC classification number: H04L5/0048 ,  H04L5/0053

Abstract: The present disclosure discloses a method and a device for transmitting data. The method includes: a UE determining, according to a preset rule, whether to transmit PUCCH and/or PUSCH and/or an SRS or not on a last symbol of a current subframe; the UE determining the PUCCH and/or the PUSCH to be transmitted on the current subframe according to availability of the last symbol of the current subframe for transmitting the PUCCH and/or the PUSCH; and the UE transmitting the PUCCH and/or the PUSCH on the current subframe and/or transmitting the SRS on the last symbol of the current subframe. In virtue of the present disclosure, it can be realized that a plurality of types of physical uplink signals/channels are simultaneously transmitted.

Abstract translation: 本公开公开了一种用于发送数据的方法和装置。 该方法包括：UE根据预设规则确定是否在当前子帧的最后一个符号上发送PUCCH和/或PUSCH和/或SRS; UE根据用于发送PUCCH和/或PUSCH的当前子帧的最后一个符号的可用性来确定要在当前子帧上发送的PUCCH和/或PUSCH; 并且UE在当前子帧上发送PUCCH和/或PUSCH，和/或在当前子帧的最后一个符号上发送SRS。 凭借本公开，可以实现同时发送多种类型的物理上行链路信号/信道。