公开(公告)号：US07616029B1

公开(公告)日：2009-11-10

申请号：US11869019

申请日：2007-10-09

申请人： William B. Andrews ,  Phillip Johnson ,  John Schadt ,  Harold Scholz

发明人： William B. Andrews ,  Phillip Johnson ,  John Schadt ,  Harold Scholz

IPC分类号： H03K5/22

CPC分类号： H03K19/20

摘要： In one embodiment of the invention, a bias signal monitor has two signal comparators that compare two (power supply) voltages at two different bias points and a logic circuit that processes the outputs from the two signal monitors to generate a bias signal monitor output signal. The logic circuit implements hysteresis-based processing such that (1) if both signal comparators are active (indicating that a first voltage is greater than the second voltage relative to both bias points), then the monitor output is active, (2) if both signal comparators are inactive (indicating that the first voltage is not greater than the second voltage relative to either bias point), then the monitor output is inactive, and (3) if one signal comparator is active and the other is inactive, then the monitor output keeps its previous value. This hysteresis characteristic prevents relatively small oscillations between the voltages from changing the monitor output.

摘要翻译： 在本发明的一个实施例中，偏置信号监视器具有两个信号比较器，其比较两个不同偏置点处的两个（电源）电压;以及逻辑电路，其处理来自两个信号监视器的输出以产生偏置信号监视输出信号。 逻辑电路实现基于滞后的处理，使得（1）如果两个信号比较器都是有效的（指示第一个电压相对于两个偏置点大于第二个电压），则监视器输出是有效的，（2）如果两个 信号比较器无效（表示第一个电压不大于相对于任一偏置点的第二个电压），则监视器输出无效，（3）如果一个信号比较器处于活动状态，另一个不起作用，则监视器 输出保持其以前的值。 这种滞后特性防止了改变监视器输出的电压之间的相对小的振荡。

公开(公告)号：US07009433B2

公开(公告)日：2006-03-07

申请号：US10447451

申请日：2003-05-28

申请人： Fulong Zhang ,  William B. Andrews ,  Phillip Johnson ,  Hal Scholz ,  Zheng (Jeff) Chen ,  John Schadt

发明人： Fulong Zhang ,  William B. Andrews ,  Phillip Johnson ,  Hal Scholz ,  Zheng (Jeff) Chen ,  John Schadt

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0805

摘要： Systems and methods are disclosed herein to implement signal delay in integrated circuits. For example, in accordance with an embodiment of the present invention, a master delay circuit may digitally control one or more slave delay cells to support various applications of a programmable logic device.

摘要翻译： 本文公开了在集成电路中实现信号延迟的系统和方法。 例如，根据本发明的实施例，主延迟电路可以数字地控制一个或多个从延迟单元以支持可编程逻辑器件的各种应用。

公开(公告)号：US07844243B1

公开(公告)日：2010-11-30

申请号：US12402751

申请日：2009-03-12

申请人： William B. Andrews ,  John Schadt

发明人： William B. Andrews ,  John Schadt

IPC分类号： H04B1/28 ,  H04B1/16

CPC分类号： H04L25/0272 ,  H04L25/0264 ,  H04L25/0294

摘要： In one embodiment of the invention, a receiver has two mux circuits, two receiver circuits, and a mixer. The muxes select first and second input signals for the receiver circuits. A p-type transistor in a transmission gate in each mux is connected (i) at its channel nodes between a pad and the mux output and (ii) to receive a control signal at its gate node. Control circuitry for the p-type transistor implements a threshold reduction filter that ensures that a maximum voltage level at the mux output is at least a threshold below the mux's power supply voltage. Based on first and second input signals, the first receiver circuit generates first and second intermediate signals, and the second receiver circuit generates third and fourth intermediate signals. The mixer circuit combines the intermediate signals to generate first and second output signals, wherein the first and second receiver circuits effectively operate over different ranges of common-mode voltages.

摘要翻译： 在本发明的一个实施例中，接收器具有两个多路复用电路，两个接收器电路和混频器。 多路复用器为接收机电路选择第一和第二输入信号。 每个多路复用器中的传输门中的p型晶体管在其沟道节点处连接（i）在焊盘和多路复用器输出之间，以及（ii）在其栅极节点处接收控制信号。 用于p型晶体管的控制电路实现阈值滤波器，其确保多路复用器输出处的最大电压电平至少低于多路复用器电源电压的阈值。 基于第一和第二输入信号，第一接收器电路产生第一和第二中间信号，第二接收器电路产生第三和第四中间信号。 混频器电路组合中间信号以产生第一和第二输出信号，其中第一和第二接收器电路有效地在不同的共模电压范围上工作。

公开(公告)号：US07605609B1

公开(公告)日：2009-10-20

申请号：US11957598

申请日：2007-12-17

申请人： William B. Andrews ,  Mou C. Lin ,  John Schadt

发明人： William B. Andrews ,  Mou C. Lin ,  John Schadt

IPC分类号： H03K19/0175

CPC分类号： H03K3/356165

摘要： In one embodiment of the invention, a programmable level shifter can be selectively configured to operate in either a high-speed mode or a low-power mode. In both modes, the level shifter converts an input signal in one power supply domain into an output signal in another power supply domain. In the high-speed mode, p-type devices are configured as a current-mirror amplifier that provides the level shifter with relatively fast switching speed. In the low-power mode, the same p-type devices are configured as a cross-coupled latch that provides the level shifter with relatively low power consumption. Selectively enabled n-type devices provide the low-power mode with larger effective n-type devices to flip the cross-coupled latch formed by the p-type devices in the low-power mode.

摘要翻译： 在本发明的一个实施例中，可编程电平转换器可被选择性地配置为以高速模式或低功率模式工作。 在两种模式中，电平移位器将一个电源域中的输入信号转换为另一个电源域中的输出信号。 在高速模式中，p型器件被配置为电流镜放大器，为电平转换器提供相对较快的开关速度。 在低功耗模式中，相同的p型器件被配置为交叉耦合的锁存器，其为电平移位器提供相对较低的功耗。 选择性使能的n型器件提供具有较大有效n型器件的低功耗模式，以在低功耗模式下翻转由p型器件形成的交叉耦合锁存器。

公开(公告)号：US07586325B1

公开(公告)日：2009-09-08

申请号：US11949130

申请日：2007-12-03

申请人： William B. Andrews ,  Mou C. Lin ,  John Schadt

发明人： William B. Andrews ,  Mou C. Lin ,  John Schadt

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/00369 ,  H03K17/14 ,  H03K19/17748 ,  H03K19/1778

摘要： In one embodiment, an integrated circuit has configurable application circuitry that operates at any one of multiple available power supply voltages. PT-control circuitry, operating at a PT reference voltage, generates a PT-control signal indicative of variations in process and temperature. Application-control circuitry controls the configuration of the application circuitry based on the selected power supply voltage for the application circuitry and the PT-control signal, where the selected power supply voltage is independent of the PT reference voltage. In one implementation, the application circuitry is an output driver having source and sink driver blocks, where driver-control circuitry controls the configuration of the source driver block based on the selected output-driver power supply voltage, a source PT-control signal, and a selected drive strength, while controlling the configuration of the sink driver block based on the selected output-driver power supply voltage, a sink PT-control signal, and a selected drive strength.

摘要翻译： 在一个实施例中，集成电路具有可操作的多个可用电源电压中的任何一个的可配置应用电路。 以PT参考电压工作的PT控制电路产生指示过程和温度变化的PT控制信号。 应用控制电路基于用于应用电路和PT控制信号的所选择的电源电压控制应用电路的配置，其中所选择的电源电压独立于PT参考电压。 在一个实现中，应用电路是具有源和接收器驱动器块的输出驱动器，其中驱动器控制电路基于所选择的输出驱动器电源电压来控制源极驱动器模块的配置，源PT控制信号和 选择的驱动强度，同时基于所选择的输出驱动器电源电压，信宿PT控制信号和选择的驱动强度来控制接收器驱动器块的配置。

公开(公告)号：US07262630B1

公开(公告)日：2007-08-28

申请号：US11194356

申请日：2005-08-01

申请人： William B. Andrews ,  Barry K. Britton ,  John Schadt ,  Mou C. Lin

发明人： William B. Andrews ,  Barry K. Britton ,  John Schadt ,  Mou C. Lin

IPC分类号： H03K19/003

CPC分类号： H03K19/17744 ,  H04L25/0278

摘要： In one embodiment of the invention, a programmable termination structure has first and second termination circuits for corresponding pads and a programmable connection therebetween. The first termination circuit supports first and second sets of termination schemes. A shared resistor is part of at least one termination scheme in each set. The first termination circuit supports a termination scheme between the first pad and a user-defined node connected to an on-chip capacitor such that first pad is connected via the termination scheme to the on-chip capacitor. Control circuitry automatically turns on and off a termination scheme for bidirectional signaling supported by the first termination circuit, wherein (1) the control circuitry turns off the termination scheme if an output buffer is configured to present outgoing signals at the first pad and (2) the control circuitry turns on the termination scheme if the output buffer is disabled in order to terminate incoming signals received at the first pad.

摘要翻译： 在本发明的一个实施例中，可编程终端结构具有用于相应焊盘的第一和第二终端电路以及它们之间的可编程连接。 第一终端电路支持第一和第二组终端方案。 共享电阻是每组中至少一个终端方案的一部分。 第一终端电路支持第一焊盘和连接到片上电容器的用户定义节点之间的终止方案，使得第一焊盘通过端接方案连接到片上电容器。 控制电路自动打开和关闭由第一终端电路支持的用于双向信令的终止方案，其中（1）如果输出缓冲器被配置为在第一焊盘处呈现输出信号，则控制电路关闭终止方案，（2） 如果禁止输出缓冲器以便终止在第一焊盘处接收到的输入信号，则控制电路接通终止方案。

公开(公告)号：US07215149B1

公开(公告)日：2007-05-08

申请号：US11012550

申请日：2004-12-15

申请人： William B. Andrews ,  Larry R. Fenstermaker ,  John Schadt ,  Mou C. Lin

发明人： William B. Andrews ,  Larry R. Fenstermaker ,  John Schadt ,  Mou C. Lin

IPC分类号： H03K19/0175

CPC分类号： H03K19/00384 ,  H03K3/356104 ,  H03K19/018521

摘要： An electrical system has a master circuit and an interface (I/F) circuit. The master circuit generates a master output signal. The I/F circuit receives an I/F input signal and a flag signal and generates an I/F output signal for application to a slave circuit, wherein the I/F input signal is based on the master output signal, and the interface circuit generates the L/F output signal either dependent on or independent of the I/F input signal as indicated by the flag signal.

摘要翻译： 电气系统具有主电路和接口（I / F）电路。 主电路产生主输出信号。 I / F电路接收I / F输入信号和标志信号，并产生用于应用于从电路的I / F输出信号，其中I / F输入信号基于主输出信号，并且接口电路 产生依赖于或独立于I / F输入信号的L / F输出信号，如标志信号所示。

公开(公告)号：US06943582B1

公开(公告)日：2005-09-13

申请号：US10671363

申请日：2003-09-25

申请人： William B. Andrews ,  Mou C. Lin ,  John Schadt

发明人： William B. Andrews ,  Mou C. Lin ,  John Schadt

IPC分类号： H03K19/177

CPC分类号： H03K19/17744

摘要： A programmable device such as a field-programmable gate array (FPGA) has programmable I/O circuitry. In one embodiment, a programmable I/O circuit (PIC) associated with at least first and second pads of the device has an output buffer that is selectively connected to the first and second pads via corresponding first and second transmission gates. The transmission gates enable an outgoing signal from the output buffer to be individually and selectively presented at the pads, while reducing the capacitive loading at each pad when the corresponding transmission gate is open (i.e., when the outgoing signal is not to be presented at that pad).

摘要翻译： 诸如现场可编程门阵列（FPGA）的可编程器件具有可编程I / O电路。 在一个实施例中，与设备的至少第一和第二焊盘相关联的可编程I / O电路（PIC）具有经由对应的第一和第二传输门选择性地连接到第一和第二焊盘的输出缓冲器。 传输门允许来自输出缓冲器的输出信号被单独地选择地呈现在焊盘处，同时当相应的传输门打开时减小每个焊盘处的容性负载（即，当不输出信号时， 垫）。

公开(公告)号：US07505752B1

公开(公告)日：2009-03-17

申请号：US11189067

申请日：2005-07-25

申请人： William B. Andrews ,  John Schadt

发明人： William B. Andrews ,  John Schadt

IPC分类号： H04B1/16 ,  H04B1/28

CPC分类号： H04L25/0272 ,  H04L25/0264 ,  H04L25/0294

摘要： In one embodiment of the invention, a receiver has two mux circuits, two receiver circuits, and a mixer. The muxes select first and second input signals for the receiver circuits. A p-type transistor in a transmission gate in each mux is connected (i) at its channel nodes between a pad and the mux output and (ii) to receive a control signal at its gate node. Control circuitry for the p-type transistor implements a threshold reduction filter that ensures that a maximum voltage level at the mux output is at least a threshold below the mux's power supply voltage. Based on first and second input signals, the first receiver circuit generates first and second intermediate signals, and the second receiver circuit generates third and fourth intermediate signals. The mixer circuit combines the intermediate signals to generate first and second output signals, wherein the first and second receiver circuits effectively operate over different ranges of common-mode voltages.

摘要翻译： 在本发明的一个实施例中，接收器具有两个多路复用电路，两个接收器电路和混频器。 多路复用器为接收机电路选择第一和第二输入信号。 每个多路复用器中的传输门中的p型晶体管在其沟道节点处连接（i）在焊盘和多路复用器输出之间，以及（ii）在其栅极节点处接收控制信号。 用于p型晶体管的控制电路实现阈值滤波器，其确保多路复用器输出处的最大电压电平至少低于多路复用器电源电压的阈值。 基于第一和第二输入信号，第一接收器电路产生第一和第二中间信号，第二接收器电路产生第三和第四中间信号。 混频器电路组合中间信号以产生第一和第二输出信号，其中第一和第二接收器电路有效地在不同的共模电压范围上工作。

公开(公告)号：US07573770B1

公开(公告)日：2009-08-11

申请号：US11778457

申请日：2007-07-16

申请人： Fulong Zhang ,  Harold Scholz ,  Larry Fenstermaker ,  John Schadt

发明人： Fulong Zhang ,  Harold Scholz ,  Larry Fenstermaker ,  John Schadt

IPC分类号： G11C7/00

CPC分类号： G06F5/06

摘要： In one embodiment of the invention, an integrated circuit, such as an FPGA, comprises a distributed FIFO architecture that supports data transfer from an external device, such as an SDRAM, via an interface that receives a non-continuous, asynchronous strobe clock and a data lane having a plurality of bit lines from the external device. The distributed FIFO architecture comprise a FIFO for each bit line and a FIFO controller. Under control of the FIFO controller, data is written into each FIFO using a FIFO write clock based on the strobe clock, while data is read out from each FIFO using a FIFO read clock based on a local reference clock of the integrated circuit. The distributed FIFO architecture is designed to handle a range of possible phase differences between the FIFO write and read clocks to safely convert from the asynchronous, non-continuous strobe domain to a local continuous clock domain.

摘要翻译： 在本发明的一个实施例中，诸如FPGA的集成电路包括分布式FIFO架构，其支持诸如SDRAM的外部设备的数据传输，所述接口接收非连续异步选通时钟和 数据通道具有来自外部设备的多个位线。 分布式FIFO架构包括用于每个位线的FIFO和FIFO控制器。 在FIFO控制器的控制下，使用基于选通时钟的FIFO写时钟将数据写入每个FIFO，而使用基于集成电路的本地参考时钟的FIFO读时钟从每个FIFO读出数据。 分布式FIFO架构旨在处理FIFO写入和读取时钟之间可能的相位差范围，以安全地将异步非连续选通域转换为本地连续时钟域。