公开(公告)号：US07616029B1

公开(公告)日：2009-11-10

申请号：US11869019

申请日：2007-10-09

申请人： William B. Andrews ,  Phillip Johnson ,  John Schadt ,  Harold Scholz

发明人： William B. Andrews ,  Phillip Johnson ,  John Schadt ,  Harold Scholz

IPC分类号： H03K5/22

CPC分类号： H03K19/20

摘要： In one embodiment of the invention, a bias signal monitor has two signal comparators that compare two (power supply) voltages at two different bias points and a logic circuit that processes the outputs from the two signal monitors to generate a bias signal monitor output signal. The logic circuit implements hysteresis-based processing such that (1) if both signal comparators are active (indicating that a first voltage is greater than the second voltage relative to both bias points), then the monitor output is active, (2) if both signal comparators are inactive (indicating that the first voltage is not greater than the second voltage relative to either bias point), then the monitor output is inactive, and (3) if one signal comparator is active and the other is inactive, then the monitor output keeps its previous value. This hysteresis characteristic prevents relatively small oscillations between the voltages from changing the monitor output.

摘要翻译： 在本发明的一个实施例中，偏置信号监视器具有两个信号比较器，其比较两个不同偏置点处的两个（电源）电压;以及逻辑电路，其处理来自两个信号监视器的输出以产生偏置信号监视输出信号。 逻辑电路实现基于滞后的处理，使得（1）如果两个信号比较器都是有效的（指示第一个电压相对于两个偏置点大于第二个电压），则监视器输出是有效的，（2）如果两个 信号比较器无效（表示第一个电压不大于相对于任一偏置点的第二个电压），则监视器输出无效，（3）如果一个信号比较器处于活动状态，另一个不起作用，则监视器 输出保持其以前的值。 这种滞后特性防止了改变监视器输出的电压之间的相对小的振荡。

公开(公告)号：US07034596B2

公开(公告)日：2006-04-25

申请号：US10365083

申请日：2003-02-11

申请人： William B. Andrews ,  Harold Scholz ,  Barry K. Britton

发明人： William B. Andrews ,  Harold Scholz ,  Barry K. Britton

IPC分类号： H03K3/00

CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0818 ,  H04L7/0041 ,  H04L7/0337

摘要： Systems and methods are disclosed to provide static and/or dynamic phase adjustments to a data signal relative to a clock signal. For example, the data signal may be delayed by a coarse delay and/or a fine delay to match the timing of the clock signal independently for each input path (e.g., per input pad). The delay may be as a function of positive and/or negative clock edges.

摘要翻译： 公开了系统和方法以相对于时钟信号为数据信号提供静态和/或动态相位调整。 例如，数据信号可以被延迟粗略的延迟和/或精细的延迟，以针对每个输入路径（例如，每个输入焊盘）独立地匹配时钟信号的定时。 延迟可以是正和/或负时钟边缘的函数。

公开(公告)号：US06952115B1

公开(公告)日：2005-10-04

申请号：US10613462

申请日：2003-07-03

申请人： William B. Andrews ,  Fulong Zhang ,  Harold Scholz

发明人： William B. Andrews ,  Fulong Zhang ,  Harold Scholz

IPC分类号： G11C7/10 ,  H03K19/173 ,  H03K19/177

CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  H03K19/17744

摘要： A programmable logic device (PLD), such as a field programmable gate array (FPGA) has a logic core surrounded on one or more sides by an input/output (I/O) interface having one or more programmable I/O buffers (PIBs). At least one PIB can be programmed to perform two or more of (a) a pass-through data input mode, (b) an input register mode; (c) a double data rate (DDR) input mode, (d) one or more demux input modes, (e) one or more DDR demux input modes. In addition or alternatively, at least one PIB can be programmed to perform two or more of (a) a pass-through data output mode, (b) an output register mode, (c) a DDR output mode, (d) one or more mux output modes, and (e) one or more DDR mux output modes. As such, devices of the present invention are flexible enough to support both low-rate and high-rate interface applications, while efficiently using device resources.

摘要翻译： 诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有通过具有一个或多个可编程I / O缓冲器（PIB）的输入/输出（I / O）接口在一侧或多侧上包围的逻辑核 ）。 至少一个PIB可以被编程为执行（a）直通数据输入模式，（b）输入寄存器模式中的两个或更多个; （c）双数据速率（DDR）输入模式，（d）一个或多个解复用器输入模式，（e）一个或多个DDR解复用器输入模式。 另外或替代地，至少一个PIB可被编程为执行（a）直通数据输出模式，（b）输出寄存器模式，（c）DDR输出模式，（d）一个或多个 更多多路输出模式，（e）一个或多个DDR多路复用器输出模式。 因此，本发明的设备足够灵活，以支持低速率和高速率的接口应用，同时有效地利用设备资源。

公开(公告)号：US06943583B1

公开(公告)日：2005-09-13

申请号：US10671378

申请日：2003-09-25

申请人： William B. Andrews ,  Mou C. Lin ,  Harold Scholz ,  Arifur Rahman

发明人： William B. Andrews ,  Mou C. Lin ,  Harold Scholz ,  Arifur Rahman

IPC分类号： H03K19/177

CPC分类号： H03K19/17744

摘要： A programmable device such as a field-programmable gate array (FPGA) has programmable I/O circuitry. In one embodiment, a programmable I/O circuit (PIC) associated with at least first and second pads of the device has an output buffer that is selectively connected to the first and second pads via corresponding first and second transmission gates. The transmission gates enable an outgoing signal from the output buffer to be individually and selectively presented at the pads, while reducing the capacitive loading at each pad when the corresponding transmission gate is open (i.e., when the outgoing signal is not to be presented at that pad).

摘要翻译： 诸如现场可编程门阵列（FPGA）的可编程器件具有可编程I / O电路。 在一个实施例中，与设备的至少第一和第二焊盘相关联的可编程I / O电路（PIC）具有经由对应的第一和第二传输门选择性地连接到第一和第二焊盘的输出缓冲器。 传输门允许来自输出缓冲器的输出信号被单独地选择地呈现在焊盘处，同时当相应的传输门打开时减小每个焊盘处的容性负载（即，当不输出信号时， 垫）。

公开(公告)号：US07009423B1

公开(公告)日：2006-03-07

申请号：US11134152

申请日：2005-05-20

申请人： William B. Andrews ,  Fulong Zhang ,  Harold Scholz

发明人： William B. Andrews ,  Fulong Zhang ,  Harold Scholz

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  H03K19/17744

摘要： A programmable logic device (PLD), such as a field programmable gate array (FPGA) has a logic core surrounded on one or more sides by an input/output (I/O) interface having one or more programmable I/O buffers (PIBs). At least one PIB can be programmed to perform two or more of (a) a pass-through data input mode, (b) an input register mode; (c) a double data rate (DDR) input mode, (d) one or more demux input modes, (e) one or more DDR demux input modes. In addition or alternatively, at least one PIB can be programmed to perform two or more of (a) a pass-through data output mode, (b) an output register mode, (c) a DDR output mode, (d) one or more mux output modes, and (e) one or more DDR mux output modes. As such, devices of the present invention are flexible enough to support both low-rate and high-rate interface applications, while efficiently using device resources.

摘要翻译： 诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有通过具有一个或多个可编程I / O缓冲器（PIB）的输入/输出（I / O）接口在一侧或多侧上包围的逻辑核 ）。 至少一个PIB可以被编程为执行（a）直通数据输入模式，（b）输入寄存器模式中的两个或更多个; （c）双数据速率（DDR）输入模式，（d）一个或多个解复用器输入模式，（e）一个或多个DDR解复用器输入模式。 另外或替代地，至少一个PIB可被编程为执行（a）直通数据输出模式，（b）输出寄存器模式，（c）DDR输出模式，（d）一个或多个 更多多路输出模式，（e）一个或多个DDR多路复用器输出模式。 因此，本发明的设备足够灵活，以支持低速率和高速率的接口应用，同时有效地利用设备资源。

公开(公告)号：US07573770B1

公开(公告)日：2009-08-11

申请号：US11778457

申请日：2007-07-16

申请人： Fulong Zhang ,  Harold Scholz ,  Larry Fenstermaker ,  John Schadt

发明人： Fulong Zhang ,  Harold Scholz ,  Larry Fenstermaker ,  John Schadt

IPC分类号： G11C7/00

CPC分类号： G06F5/06

摘要： In one embodiment of the invention, an integrated circuit, such as an FPGA, comprises a distributed FIFO architecture that supports data transfer from an external device, such as an SDRAM, via an interface that receives a non-continuous, asynchronous strobe clock and a data lane having a plurality of bit lines from the external device. The distributed FIFO architecture comprise a FIFO for each bit line and a FIFO controller. Under control of the FIFO controller, data is written into each FIFO using a FIFO write clock based on the strobe clock, while data is read out from each FIFO using a FIFO read clock based on a local reference clock of the integrated circuit. The distributed FIFO architecture is designed to handle a range of possible phase differences between the FIFO write and read clocks to safely convert from the asynchronous, non-continuous strobe domain to a local continuous clock domain.

摘要翻译： 在本发明的一个实施例中，诸如FPGA的集成电路包括分布式FIFO架构，其支持诸如SDRAM的外部设备的数据传输，所述接口接收非连续异步选通时钟和 数据通道具有来自外部设备的多个位线。 分布式FIFO架构包括用于每个位线的FIFO和FIFO控制器。 在FIFO控制器的控制下，使用基于选通时钟的FIFO写时钟将数据写入每个FIFO，而使用基于集成电路的本地参考时钟的FIFO读时钟从每个FIFO读出数据。 分布式FIFO架构旨在处理FIFO写入和读取时钟之间可能的相位差范围，以安全地将异步非连续选通域转换为本地连续时钟域。

公开(公告)号：US07808855B1

公开(公告)日：2010-10-05

申请号：US12538810

申请日：2009-08-10

申请人： Fulong Zhang ,  Harold Scholz ,  Larry Fenstermaker ,  John Schadt

发明人： Fulong Zhang ,  Harold Scholz ,  Larry Fenstermaker ,  John Schadt

IPC分类号： G11C7/00

CPC分类号： G06F5/06

摘要： In one embodiment, an integrated circuit such as an FPGA includes one or more data I/O blocks, one or more FIFOs, and a FIFO controller. At least one data I/O block receives an incoming bit stream from an external device. At least one FIFO is connected to receive a corresponding incoming bit stream from a corresponding data I/O block. The FIFO controller controls operations of the one or more FIFOs, such that (i) bits from the corresponding data I/O block are written into the at least one FIFO using a FIFO write clock that is based on an incoming clock signal and (ii) bits are read out from the at least one FIFO using a FIFO read clock that is based on a local reference clock signal.

摘要翻译： 在一个实施例中，诸如FPGA的集成电路包括一个或多个数据I / O块，一个或多个FIFO和FIFO控制器。 至少一个数据I / O块从外部设备接收输入位流。 连接至少一个FIFO以从相应的数据I / O块接收相应的输入位流。 FIFO控制器控制一个或多个FIFO的操作，使得（i）来自对应数据I / O块的位被使用基于输入时钟信号的FIFO写入时钟写入到至少一个FIFO中，并且（ii ）位使用基于本地参考时钟信号的FIFO读时钟从至少一个FIFO读出。

公开(公告)号：US07132903B1

公开(公告)日：2006-11-07

申请号：US10613460

申请日：2003-07-03

申请人： Phillip Johnson ,  Gary Powell ,  Harold Scholz

发明人： Phillip Johnson ,  Gary Powell ,  Harold Scholz

IPC分类号： H03L1/00 ,  H03B27/00

CPC分类号： H03K3/0322 ,  H03K5/133 ,  H03K2005/00208 ,  H03L7/0812 ,  H03L7/0995

摘要： A set of interconnected delay stages, such as a voltage-controlled oscillator, has switch-controlled load circuitry connected to each output of each delay stage in the oscillator ring. In one embodiment, for each delay stage output, the switch-controlled load circuitry includes a switch, a transistor, and a current source. The switch is connected between the corresponding delay stage output and the transistor gate, the current source is connected between a power supply and the transistor drain, and the transistor source is connected to ground. In such a configuration, the transistor's gate-to-source capacitance can be applied to the corresponding delay stage output by closing the switch, for example, for lower-frequency operations. In addition, the output impedance of the current source decouples the capacitive load from the power supply, thereby substantially shielding the oscillator ring from noise in the power supply.

摘要翻译： 一组互连的延迟级，例如压控振荡器，具有连接到振荡器环中每个延迟级的每个输出的开关控制负载电路。 在一个实施例中，对于每个延迟级输出，开关控制的负载电路包括开关，晶体管和电流源。 开关连接在相应的延迟级输出和晶体管栅极之间，电流源连接在电源和晶体管漏极之间，晶体管源连接到地。 在这种配置中，例如，对于较低频率的操作，晶体管的栅极 - 源极电容可以被施加到相应的延迟级输出。 此外，电流源的输出阻抗使电容负载与电源分离，从而基本上屏蔽振荡器环免受电源中的噪声。

公开(公告)号：US20070182445A1

公开(公告)日：2007-08-09

申请号：US11346817

申请日：2006-02-03

申请人： Zheng Chen ,  Barry Britton ,  Harold Scholz

发明人： Zheng Chen ,  Barry Britton ,  Harold Scholz

IPC分类号： H03K19/177

CPC分类号： G06F17/5054

摘要： In one embodiment, a programmable logic device includes: a multiplexer adapted to select a compressed configuration bitstream from a plurality of external serial interface memories; a serial interface processor adapted to command the bitstream selection by the multiplexer; and a bitstream decompressor adapted to decompress the selected configuration bitstream into a decompressed configuration bitstream.

摘要翻译： 在一个实施例中，可编程逻辑器件包括：多路复用器，适于从多个外部串行接口存储器中选择压缩配置比特流; 串行接口处理器，适于通过多路复用器命令比特流选择; 以及适于将所选配置比特流解压缩为解压配置比特流的比特流解压缩器。

公开(公告)号：US20070109880A1

公开(公告)日：2007-05-17

申请号：US11281651

申请日：2005-11-17

申请人： Fulong Zhang ,  Harold Scholz

发明人： Fulong Zhang ,  Harold Scholz

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/222

摘要： When certain digital circuit devices receive data bus signals, I/O interfaces need to sample the data signals during a time when these signals are both valid and stable. Typically, the data signals are sampled at a time corresponding to a point halfway between rising and falling edges of a reference clock signal associated with the data bus, which sampling time corresponds to a 90-degree phase shift of the reference clock signal. In one embodiment of the invention, a delay count generator determines a delay value corresponding to a quarter cycle (i.e., 90 degrees) of the reference clock signal. In making this determination, a counter counts the number of clock cycles of an internally generated, relatively high-frequency clock signal, where the number corresponds to a specified portion (e.g., one half) of a period of a divided-down version of the reference clock signal. That number can then be used to generate the 90-degree delay value.

摘要翻译： 当某些数字电路设备接收数据总线信号时，I / O接口需要在这些信号有效和稳定的时间内采样数据信号。 通常，数据信号在对应于与数据总线相关联的参考时钟信号的上升沿和下降沿之间的点相对应的时间被采样，该采样时间对应于参考时钟信号的90度相移。 在本发明的一个实施例中，延迟计数发生器确定对应于参考时钟信号的四分之一周期（即，90度）的延迟值。 在进行该确定时，计数器对内部产生的相对高频时钟信号的时钟周期数进行计数，其中数字对应于分割版本的时间段的指定部分（例如，一半） 参考时钟信号。 然后可以使用该数字来产生90度延迟值。