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    Memory having sense time of variable duration
    2.
    发明授权
    Memory having sense time of variable duration 有权
    具有可变持续时间的感觉时间的存储器

    公开(公告)号：US07668029B2

    公开(公告)日：2010-02-23

    申请号：US11464124

    申请日：2006-08-11

    申请人： William C. Moyer ,  Perry H. Pelley, III

    发明人： William C. Moyer ,  Perry H. Pelley, III

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C11/413 ,  G11C2207/2281

    摘要： In one form a memory and method thereof has a memory array having a plurality of memory cells. A bit line precharge operation is based on a clock edge of an external clock signal. A word line is selected after the beginning of the precharge operation. A sense operation is begun after enabling the word line, where the sense operation is for sensing a logic state of a memory cell. A data bit is output from the memory array corresponding to the sensed logic state of the memory cell. In one form the bit line precharge operation further comprises the bit line precharge operation having a predetermined duration that is independent of the clock signal, and the sense operation begins a predetermined delay time after enabling the word line, the sense operation having a variable duration.

    摘要翻译： 在一种形式中，其存储器及其方法具有具有多个存储单元的存储器阵列。 位线预充电操作基于外部时钟信号的时钟边沿。 在预充电操作开始之后选择字线。 在启用字线之后开始感测操作，其中感测操作用于感测存储器单元的逻辑状态。 从与存储单元的检测到的逻辑状态对应的存储器阵列输出数据位。 在一种形式中，位线预充电操作还包括具有与时钟信号无关的预定持续时间的位线预充电操作，并且感测操作在使能字线之后开始预定的延迟时间，感测操作具有可变持续时间。

    Testing of multiple integrated circuits
    3.
    发明授权
    Testing of multiple integrated circuits 有权
    多集成电路测试

    公开(公告)号：US08294483B2

    公开(公告)日：2012-10-23

    申请号：US12130173

    申请日：2008-05-30

    申请人： Lucio F. C. Pessoa ,  Perry H. Pelley, III

    发明人： Lucio F. C. Pessoa ,  Perry H. Pelley, III

    IPC分类号： G01R31/26 ,  G01R31/28

    CPC分类号： G01R31/2884 ,  G01R31/3025

    摘要： A testing system includes a tester probe and a plurality of integrated circuits. Tests are broadcast to the plurality of integrated circuits using carrierless ultra wideband (UWB) radio frequency (RF). All of the plurality of integrated circuits receive, at the same time, test input signals by way of carrierless UWB RF and all of the plurality of integrated circuits run tests and provide results based on the test input signals. Thus, the plurality of integrated circuits are tested simultaneously which significantly reduces test time. Also the tests are not inhibited by physical contact with the integrated circuits.

    摘要翻译： 测试系统包括测试仪探头和多个集成电路。 使用无载波超宽带（UWB）射频（RF）将测试广播到多个集成电路。 所有多个集成电路同时接收通过无载波UWB RF测试输入信号，并且所有多个集成电路都运行测试并基于测试输入信号提供结果。 因此，同时测试多个集成电路，这大大减少了测试时间。 此外，与集成电路的物理接触也不会妨碍测试。

    Memory with level shifting word line driver and method thereof
    4.
    发明授权
    Memory with level shifting word line driver and method thereof 有权
    具有电平转换字线驱动器的存储器及其方法

    公开(公告)号：US07440354B2

    公开(公告)日：2008-10-21

    申请号：US11433998

    申请日：2006-05-15

    申请人： Thomas W. Liston ,  Shahnaz P. Chowdhury-Nagle ,  Perry H. Pelley, III

    发明人： Thomas W. Liston ,  Shahnaz P. Chowdhury-Nagle ,  Perry H. Pelley, III

    IPC分类号： G11C7/00

    CPC分类号： G11C8/08 ,  G11C5/144 ,  G11C8/10

    摘要： A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.

    摘要翻译： 存储器包括包括多个字线的位单元阵列和具有提供预解码值的输出的地址解码电路。 地址解码电路包括具有第一栅极氧化物厚度的第一多个晶体管。 存储器还包括字线驱动器电路，其具有耦合到地址解码电路的输出的输入和多个输出，每个输出耦合到多个字线中的相应字线。 字线驱动器包括具有大于第一栅极氧化物厚度的第二栅极氧化物厚度的第二多个晶体管。 还提供了一种操作存储器的方法。

    Sense amplifier
    5.
    发明授权
    Sense amplifier 失效
    感应放大器

    公开(公告)号：US4551641A

    公开(公告)日：1985-11-05

    申请号：US554517

    申请日：1983-11-23

    申请人： Perry H. Pelley, III

    发明人： Perry H. Pelley, III

    IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/4091 ,  H03K5/24

    CPC分类号： G11C7/065 ,  G11C11/4091

    摘要： A sense amplifier is coupled to a pair of bit lines for detecting and amplifying a voltage differential therebetween. The sense amplifier has a first differential amplifier coupled to the pair of bit lines enabled in response to a first signal. The sense amplifier also has a second differential amplifier coupled to the pair of bit lines which is enabled a predetermined time duration following the occurrence of the first signal.

    摘要翻译： 读出放大器耦合到一对位线，用于检测和放大它们之间的电压差。 读出放大器具有耦合到响应于第一信号使能的一对位线对的第一差分放大器。 读出放大器还具有耦合到一对位线的第二差分放大器，其在第一信号的出现之后被允许预定的持续时间。

    Coherency groups of serially coupled processing cores propagating coherency information containing write packet to memory
    6.
    发明授权
    Coherency groups of serially coupled processing cores propagating coherency information containing write packet to memory 有权
    串行耦合处理核心的一致性组将包含写入包的一致性信息传播到存储器

    公开(公告)号：US08090913B2

    公开(公告)日：2012-01-03

    申请号：US12972878

    申请日：2010-12-20

    申请人： Perry H. Pelley, III ,  George P. Hoekstra ,  Lucio F. Pessoa

    发明人： Perry H. Pelley, III ,  George P. Hoekstra ,  Lucio F. Pessoa

    IPC分类号： G06F12/08

    CPC分类号： G06F15/16

    摘要： A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet switch. The packet switch is coupled to a memory. The first plurality of cores and the packet switch are on an integrated circuit. The memory may or may not be on the integrated circuit. In another aspect a second plurality of cores in a second coherency group is coupled to the packet switch. The cores of the first and second pluralities may be reconfigured to form or become part of coherency groups different from the first and second coherency groups.

    摘要翻译： 系统在第一相干组中具有第一多个核心。 每个核心以数据包传输数据。 核心直接串联耦合以形成串行路径。 数据包沿串行路径传输。 串行路径在一端耦合到分组交换机。 分组交换机耦合到存储器。 第一多个核心和分组交换机在集成电路上。 存储器可能集成在或不在集成电路上。 在另一方面，第二一致性组中的第二多个核心耦合到分组交换机。 可重新配置第一和第二多个的核心以形成或成为不同于第一和第二一致性组的一致性组的一部分。

    Groups of serially coupled processor cores propagating memory write packet while maintaining coherency within each group towards a switch coupled to memory partitions
    7.
    发明授权
    Groups of serially coupled processor cores propagating memory write packet while maintaining coherency within each group towards a switch coupled to memory partitions 有权
    串联耦合的处理器核心组传播存储器写入包，同时保持每个组内的一致性，转向耦合到存储器分区的交换机

    公开(公告)号：US07941637B2

    公开(公告)日：2011-05-10

    申请号：US12103250

    申请日：2008-04-15

    申请人： Perry H. Pelley, III ,  George P. Hoekstra ,  Lucio F. C. Pessoa

    发明人： Perry H. Pelley, III ,  George P. Hoekstra ,  Lucio F. C. Pessoa

    IPC分类号： G06F15/80

    CPC分类号： G06F15/16

    摘要： A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet switch. The packet switch is coupled to a memory. The first plurality of cores and the packet switch are on an integrated circuit. The memory may or may not be on the integrated circuit. In another aspect a second plurality of cores in a second coherency group is coupled to the packet switch. The cores of the first and second pluralities may be reconfigured to form or become part of coherency groups different from the first and second coherency groups.

    摘要翻译： 系统在第一相干组中具有第一多个核心。 每个核心以数据包传输数据。 核心直接串联耦合以形成串行路径。 数据包沿串行路径传输。 串行路径在一端耦合到分组交换机。 分组交换机耦合到存储器。 第一多个核心和分组交换机在集成电路上。 存储器可能集成在或不在集成电路上。 在另一方面，第二一致性组中的第二多个核心耦合到分组交换机。 可重新配置第一和第二多个的核心以形成或成为不同于第一和第二一致性组的一致性组的一部分。

    MEMORY WITH LEVEL SHIFTING WORD LINE DRIVER AND METHOD THEREOF
    8.
    发明申请
    MEMORY WITH LEVEL SHIFTING WORD LINE DRIVER AND METHOD THEREOF 有权
    具有水平移位字线驱动器的记忆及其方法

    公开(公告)号：US20090021990A1

    公开(公告)日：2009-01-22

    申请号：US12209477

    申请日：2008-09-12

    申请人： Thomas W. Liston ,  Shahnaz P. Chowdhury-Nagle ,  Perry H. Pelley, III

    发明人： Thomas W. Liston ,  Shahnaz P. Chowdhury-Nagle ,  Perry H. Pelley, III

    IPC分类号： G11C7/00 ,  G11C8/08 ,  G11C5/14

    CPC分类号： G11C8/08 ,  G11C5/144 ,  G11C8/10

    摘要： A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.

    摘要翻译： 存储器包括包括多个字线的位单元阵列和具有提供预解码值的输出的地址解码电路。 地址解码电路包括具有第一栅极氧化物厚度的第一多个晶体管。 存储器还包括字线驱动器电路，其具有耦合到地址解码电路的输出的输入和多个输出，每个输出耦合到多个字线中的相应字线。 字线驱动器包括具有大于第一栅极氧化物厚度的第二栅极氧化物厚度的第二多个晶体管。 还提供了一种操作存储器的方法。

    Memory device with sense amplifier and self-timed latch
    9.
    发明授权
    Memory device with sense amplifier and self-timed latch 有权
    具有读出放大器和自定时锁存器的存储器件

    公开(公告)号：US06862208B2

    公开(公告)日：2005-03-01

    申请号：US10412490

    申请日：2003-04-11

    申请人： Jeremiah T. C. Palmer ,  Perry H. Pelley, III

    发明人： Jeremiah T. C. Palmer ,  Perry H. Pelley, III

    IPC分类号： G11C11/419 ,  G11C11/00

    CPC分类号： G11C11/419

    摘要： A memory device (201) includes a plurality of memory cells (203), bit lines, word lines, a sense amplifier (314), and a self-timed latch (215). The sense amplifier (314), responsive to a sense enable signal, is for sensing and amplifying a voltage on the bit lines corresponding to a stored logic state of a selected one of the plurality of memory cells. An isolation circuit (306, 308) is coupled between the bit lines (205 and 207) and the sense amplifier (314). The isolation circuit (306, 308) is for decoupling the selected one of the plurality of memory cells from the sense amplifier (314) at about the same time that the sense enable signal is asserted. A self-timed latch (215) is coupled to the sense amplifier (314). The self-timed latch (215) does not receive a clock signal and is responsive to only the amplified voltage.

    摘要翻译： 存储器件（201）包括多个存储器单元（203），位线，字线，读出放大器（314）和自定时锁存器（215）。 感测放大器（314）响应于感测使能信号，用于感测和放大对应于多个存储器单元中所选择的一个的存储的逻辑状态的位线上的电压。 隔离电路（306,308）耦合在位线（205和207）与读出放大器（314）之间。 隔离电路（306,308）用于在与感测使能信号被断言的大约相同的时间将多个存储器单元中的所选择的一个与读出放大器（314）去耦合。 自定时锁存器（215）耦合到读出放大器（314）。 自定时锁存器（215）不接收时钟信号并仅对放大的电压作出响应。

    Using delay to obtain high speed current driver circuit
    10.
    发明授权
    Using delay to obtain high speed current driver circuit 失效
    使用延时获得高速电流驱动电路

    公开(公告)号：US5278464A

    公开(公告)日：1994-01-11

    申请号：US892834

    申请日：1992-06-02

    申请人： Perry H. Pelley, III ,  Hamed Ghassemi

    发明人： Perry H. Pelley, III ,  Hamed Ghassemi

    IPC分类号： H03K19/013 ,  H03K19/086

    CPC分类号： H03K19/0136 ,  H03K19/086

    摘要： A current driver circuit (10) sources current to an output node (N4) in response to an input signal (VI) being a logic high. The current driver circuit (10) utilizes a current source (16) which sinks current from the output node (N4) in response to the input signal (VI) switching from a logic high to a logic low. The current source (16) is deactivated for a predetermined time delay after the input signal (Vi) switches from a logic high to a logic low.

    摘要翻译： 电流驱动器电路（10）响应于逻辑高的输入信号（VI）将电流供给到输出节点（N4）。 当前的驱动器电路（10）利用电流源（16），其响应于从逻辑高电平切换到逻辑低电平的输入信号（VI），从电流源输出来自输出节点（N4）的电流。 在输入信号（Vi）从逻辑高电平切换到逻辑低电平之后，电流源（16）被停用预定的时间延迟。