公开(公告)号：US20100156459A1

公开(公告)日：2010-06-24

申请号：US12716469

申请日：2010-03-03

申请人： William C. Plants ,  Suhail Zain ,  Joel Landry ,  Gregory W. Bakker ,  Tomek P. Jasionowski

发明人： William C. Plants ,  Suhail Zain ,  Joel Landry ,  Gregory W. Bakker ,  Tomek P. Jasionowski

IPC分类号： H03K19/177 ,  H03L7/06

CPC分类号： H03K5/131 ,  H03K2005/00123 ,  H03K2005/0013 ,  H03K2005/00143 ,  H03K2005/00156 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/10

摘要： A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.

摘要翻译： 补偿过程，电压和温度变化的延迟线包括被配置为将数字信号延迟数字信号的时钟周期的延迟锁定环（DLL），该DLL包括布置为多个级联子串的DLL延迟线 为了响应于数字控制信号，延迟每个子延迟线提供多个延迟量子中的一个。 分馏电路被配置为产生作为数字控制信号的一部分的数字延迟线控制信号。 数字延迟线被布置为多个级联子延迟线，每个子延迟线响应于数字延迟线控制信号提供多个延迟量子中的一个。

公开(公告)号：US08067959B2

公开(公告)日：2011-11-29

申请号：US12716469

申请日：2010-03-03

申请人： William C. Plants ,  Suhail Zain ,  Joel Landry ,  Gregory W. Bakker ,  Tomek P. Jasinoski

发明人： William C. Plants ,  Suhail Zain ,  Joel Landry ,  Gregory W. Bakker ,  Tomek P. Jasinoski

IPC分类号： H03K19/173 ,  H03K25/00

CPC分类号： H03K5/131 ,  H03K2005/00123 ,  H03K2005/0013 ,  H03K2005/00143 ,  H03K2005/00156 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/10

摘要： A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.

摘要翻译： 补偿过程，电压和温度变化的延迟线包括被配置为将数字信号延迟数字信号的时钟周期的延迟锁定环（DLL），该DLL包括布置为多个级联子串的DLL延迟线 为了响应于数字控制信号，延迟每个子延迟线提供多个延迟量子中的一个。 分馏电路被配置为产生作为数字控制信号的一部分的数字延迟线控制信号。 数字延迟线被布置为多个级联子延迟线，每个子延迟线响应于数字延迟线控制信号提供多个延迟量子中的一个。

公开(公告)号：US07701246B1

公开(公告)日：2010-04-20

申请号：US12175399

申请日：2008-07-17

申请人： William C. Plants ,  Suhail Zain ,  Joel Landry ,  Gregory W. Bakker ,  Tomek Jasionowski

发明人： William C. Plants ,  Suhail Zain ,  Joel Landry ,  Gregory W. Bakker ,  Tomek Jasionowski

IPC分类号： G06F7/38 ,  H03K19/173

CPC分类号： H03K5/131 ,  H03K2005/00123 ,  H03K2005/0013 ,  H03K2005/00143 ,  H03K2005/00156 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/10

摘要： A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.

摘要翻译： 补偿过程，电压和温度变化的延迟线包括被配置为将数字信号延迟数字信号的时钟周期的延迟锁定环（DLL），该DLL包括布置为多个级联子串的DLL延迟线 为了响应于数字控制信号，延迟每个子延迟线提供多个延迟量子中的一个。 分馏电路被配置为产生作为数字控制信号的一部分的数字延迟线控制信号。 数字延迟线被布置为多个级联子延迟线，每个子延迟线响应于数字延迟线控制信号提供多个延迟量子中的一个。

公开(公告)号：US5698992A

公开(公告)日：1997-12-16

申请号：US746554

申请日：1996-11-13

申请人： Khaled A. El Ayat ,  Gregory W. Bakker ,  Jung-Cheun Lien ,  William C. Plants ,  Sinan Kaptanoglu ,  Runip Gopisetty ,  King W. Chan ,  Marko Chew

发明人： Khaled A. El Ayat ,  Gregory W. Bakker ,  Jung-Cheun Lien ,  William C. Plants ,  Sinan Kaptanoglu ,  Runip Gopisetty ,  King W. Chan ,  Marko Chew

IPC分类号： H03K19/177 ,  G01R31/28 ,  G01R31/3185 ,  H03K19/173

CPC分类号： G01R31/2884 ,  G01R31/318519 ,  H03K19/17704 ,  H03K19/17728

摘要： A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

摘要翻译： 用户可编程门阵列架构包括可包括一个或多个组合和/或顺序逻辑电路的逻辑功能模块阵列。 包括多个水平和垂直通用互连通道的互连架构，每个通道互连通道包括多个互连导体，其中一些互连导体可能被分段，其被施加在阵列上。 互连导体中的单个导体可通过用户可编程互连元件彼此连接并连接到逻辑功能模块的输入和输出端。 包括本地互连通道的本地互连架构也被施加在阵列上。 每个局部互连通道包括多个局部互连导体并且在相邻的逻辑功能模块对之间运行。

公开(公告)号：US5952847A

公开(公告)日：1999-09-14

申请号：US673701

申请日：1996-06-25

申请人： William C. Plants ,  Gregory W. Bakker

发明人： William C. Plants ,  Gregory W. Bakker

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H03K19/0175 ,  H03K19/0185

CPC分类号： H03K19/018521

摘要： The output buffer circuit according to the present invention is connected to an I/O pad of the integrated circuit. The output buffer circuit includes an output totem pole, a level shifter and enable logic. The output totem pole has a first input connected to the level shifter and a second input connected to the enable logic. The output of the totem pole is connected to an I/O pad. The totem pole includes a pullup transistor connected to 3.3 volt Vcc and a pulldown transistor connected to ground. In a first embodiment of the invention, the pullup transistor in the totem pole is an N-channel MOS transistor, and in a second embodiment of the invention, the pullup transistor in the totem pole is a P-channel MOS transistor formed in an N-well tied to the 5 volt Vcc. In the first embodiment of the present invention, the N-Channel MOS pullup transistor is turned on by a 5 volt signal from the level shifter. In the second embodiment of the present invention, the P-Channel MOS pullup transistor is turned on by a ground level signal from the level shifter. The enable logic drives the output of the totem pole in response to input signals to the enable logic. The inputs to the enable logic are a Data input, a Global enable input and an Output enable input.

摘要翻译： 根据本发明的输出缓冲器电路连接到集成电路的I / O焊盘。 输出缓冲电路包括输出图腾柱，电平移位器和使能逻辑。 输出图腾柱具有连接到电平移位器的第一输入端和连接到使能逻辑的第二输入端。 图腾柱的输出连接到I / O焊盘。 图腾柱包括连接到3.3伏Vcc的上拉晶体管和连接到地的下拉晶体管。 在本发明的第一实施例中，图腾柱中的上拉晶体管是N沟道MOS晶体管，在本发明的第二实施例中，图腾柱中的上拉晶体管是形成在N沟道MOS晶体管中的P沟道MOS晶体管 - 连接到5伏Vcc。 在本发明的第一实施例中，N沟道MOS上拉晶体管由来自电平移位器的5伏特信号导通。 在本发明的第二实施例中，P沟道MOS上拉晶体管由来自电平移位器的接地电平信号导通。 响应于使能逻辑的输入信号，使能逻辑驱动图腾柱的输出。 使能逻辑的输入是数据输入，全局使能输入和输出使能输入。

公开(公告)号：US5477165A

公开(公告)日：1995-12-19

申请号：US332550

申请日：1994-12-28

申请人： Khaled A. ElAyat ,  Gregory W. Bakker ,  Jung-Cheun Lien ,  William C. Plants ,  Sinan Kaptanoglu ,  Runip Gopisetty ,  King W. Chan ,  Marko Chew

发明人： Khaled A. ElAyat ,  Gregory W. Bakker ,  Jung-Cheun Lien ,  William C. Plants ,  Sinan Kaptanoglu ,  Runip Gopisetty ,  King W. Chan ,  Marko Chew

IPC分类号： H03K19/177 ,  G01R31/28 ,  G01R31/3185 ,  H03K19/173

CPC分类号： G01R31/2884 ,  G01R31/318519 ,  H03K19/17704 ,  H03K19/17728

摘要： A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

摘要翻译： 用户可编程门阵列架构包括可包括一个或多个组合和/或顺序逻辑电路的逻辑功能模块阵列。 包括多个水平和垂直通用互连通道的互连架构，每个通道互连通道包括多个互连导体，其中一些互连导体可能被分段，其被施加在阵列上。 互连导体中的单个导体可通过用户可编程互连元件彼此连接并连接到逻辑功能模块的输入和输出端。 包括本地互连通道的本地互连架构也被施加在阵列上。 每个局部互连通道包括多个局部互连导体并且在相邻的逻辑功能模块对之间运行。

公开(公告)号：US5606267A

公开(公告)日：1997-02-25

申请号：US522945

申请日：1995-09-01

申请人： Khaled A. El Ayat ,  Gregory W. Bakker ,  Jung-Cheun Lien ,  William C. Plants ,  Sinan Kaptanoglu ,  Runip Gopisetty ,  King W. Chan ,  Marko Chew

发明人： Khaled A. El Ayat ,  Gregory W. Bakker ,  Jung-Cheun Lien ,  William C. Plants ,  Sinan Kaptanoglu ,  Runip Gopisetty ,  King W. Chan ,  Marko Chew

IPC分类号： H03K19/177 ,  G01R31/28 ,  G01R31/3185 ,  H03K19/173

CPC分类号： G01R31/2884 ,  G01R31/318519 ,  H03K19/17704 ,  H03K19/17728

摘要： A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

公开(公告)号：US20100134142A1

公开(公告)日：2010-06-03

申请号：US12701068

申请日：2010-02-05

申请人： Gregory Bakker ,  Joel Landry ,  William C. Plants

发明人： Gregory Bakker ,  Joel Landry ,  William C. Plants

IPC分类号： H03K19/177

CPC分类号： H03K19/1733 ,  G06F17/5054

摘要： A computer program product in a computer-readable medium for use in a microcontroller-based control system in a programmable logic integrated circuit device. The computer program product comprises first instructions for initializing the device, second instructions for reading programming data from a data source external to the programmable logic integrated circuit device, third instructions for transferring the programming data into control elements internal to the device. Provision is made for fourth instructions for saving a part of the internal logic state of the user logic programmed into the device into a non-volatile memory block and for fifth instructions for restoring a part of the internal logic state of the user logic programmed into the device from a non-volatile memory block. The device comprises a microcontroller block and a programmable logic block with programming circuitry, and has a sub-bus which couples the microcontroller block to the programming circuitry.

摘要翻译： 一种用于可编程逻辑集成电路装置中的基于微控制器的控制系统的计算机可读介质中的计算机程序产品。 计算机程序产品包括用于初始化设备的第一指令，用于从可编程逻辑集成电路设备外部的数据源读取编程数据的第二指令，用于将编程数据传送到设备内部的控制元件中的第三指令。 提供了用于将编程到设备中的用户逻辑的内部逻辑状态的一部分保存到非易失性存储器块中的第四指令，以及用于恢复被编程到该非易失性存储器块中的用户逻辑的内部逻辑状态的一部分的第五指令 设备从非易失性存储器块。 该器件包括微控制器模块和具有编程电路的可编程逻辑模块，并且具有将微控制器模块耦合到编程电路的子总线。

公开(公告)号：US08446170B2

公开(公告)日：2013-05-21

申请号：US13463232

申请日：2012-05-03

申请人： Joel Landry ,  Jonathan Greene ,  William C. Plants ,  Wenyi Feng

发明人： Joel Landry ,  Jonathan Greene ,  William C. Plants ,  Wenyi Feng

IPC分类号： H03K19/177

CPC分类号： H03K19/177 ,  G11C8/16 ,  H03K19/1776

摘要： A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.

摘要翻译： 公开了一种适用于现场可编程门阵列集成电路器件的随机存取存储器电路。 FPGA具有可编程阵列，其具有逻辑模块和路由互连，可编程地耦合到逻辑模块和RAM电路。 RAM电路具有三个端口：第一可读端口，第二可读端口和可写入端口。 读端口可以是可编程同步的或异步的，并且具有可编程可旁路输出流水线寄存器。 RAM电路特别适用于实现寄存器文件。 还描述了一种新颖的互连方法。

公开(公告)号：US07683660B1

公开(公告)日：2010-03-23

申请号：US12023299

申请日：2008-01-31

申请人： Gregory Bakker ,  Joel Landry ,  William C. Plants

发明人： Gregory Bakker ,  Joel Landry ,  William C. Plants

IPC分类号： H03K19/173

CPC分类号： H03K19/1733 ,  G06F17/5054

摘要： A computer program product in a computer-readable medium for use in a microcontroller-based control system in a programmable logic integrated circuit device is disclosed. The computer program product comprises first instructions for initializing the device, second instructions for reading programming data from a data source external to the programmable logic integrated circuit device, third instructions for transferring the programming data into control elements internal to the programmable logic integrated circuit device. Provision is made for fourth instructions for saving at least a part of the internal logic state of the user logic programmed into the programmable logic integrated circuit device into a non-volatile memory block and for fifth instructions for restoring at least a part of the internal logic state of the user logic programmed into the programmable logic integrated circuit device from a non-volatile memory block. The programmable logic integrated circuit device, comprises a microcontroller block and a programmable logic block with programming circuitry, and has a sub-bus which couples the microcontroller block to the programming circuitry.

摘要翻译： 公开了一种用于可编程逻辑集成电路装置中基于微控制器的控制系统的计算机可读介质中的计算机程序产品。 计算机程序产品包括用于初始化设备的第一指令，用于从可编程逻辑集成电路器件外部的数据源读取编程数据的第二指令，用于将编程数据传送到可编程逻辑集成电路器件内部的控制元件的第三指令。 规定了第四条指令，用于将编程到可编程逻辑集成电路设备中的用户逻辑的内部逻辑状态的至少一部分保存到非易失性存储器块中，以及用于恢复内部逻辑的至少一部分的第五指令 从非易失性存储器块编程到可编程逻辑集成电路器件中的用户逻辑状态。 可编程逻辑集成电路器件包括微控制器模块和具有编程电路的可编程逻辑模块，并且具有将微控制器模块耦合到编程电路的子总线。