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公开(公告)号：US4074353A
公开(公告)日：1978-02-14
申请号：US689014
申请日：1976-05-24
CPC分类号： G06F9/462
摘要： A plurality of trap save areas are linked to form a pool of such areas from which an area may be loaded with context from various sources in response to a trap condition, such as the addressing of unuseable memory, the loaded area unlinked from the pool, and various pointers changed to reflect such unlinking. The unlinked area is associated with the process which was executing at the time of the occurrence of the trap condition by effectively being coupled to the interrupt level of such process. Independent of the interrupt level, a trap handler routine, specific to the nature of the trap condition, is executed following which the unlinked area is returned to the pool and the various pointers changed to reflect such return.
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公开(公告)号：US4047247A
公开(公告)日：1977-09-06
申请号：US674517
申请日：1976-04-07
CPC分类号： G06F9/355
摘要： A final effective address of an operand is generated in a microprogrammed data processing system by use of a base address register which may include an unindexed address, an index register which may include an index address value, an instruction register which may include an instruction word, which instruction word provides control over the addressing of a control store dependent upon the state of a selected one of a plurality of test conditions. The addressed control store word provides signals for controlling the operation of the system, including the branching between such major operations as instruction fetching, addressing, reading, writing, and execution as well as branching between minor operations which are included in the major operations.
摘要翻译： 操作数的最终有效地址在微程序数据处理系统中通过使用可包括无索引地址的基址寄存器，可包括索引地址值的索引寄存器，可包括指令字的指令寄存器， 该指令字取决于多个测试条件中所选择的一个的状态来提供对控制存储器的寻址的控制。 寻址的控制存储字提供用于控制系统操作的信号，包括在诸如指令获取，寻址，读取，写入和执行之类的主要操作之间的分支以及在主要操作中包括的次要操作之间的分支。
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3.发明授权Buffered address stack register with parallel input registers and overflow protection 失效缓冲地址堆栈寄存器具有并行输入寄存器和溢出保护
公开(公告)号：US5161217A
公开(公告)日：1992-11-03
申请号：US418084
申请日：1989-10-06
IPC分类号： G06F7/78
CPC分类号： G06F7/78
摘要： A last-in, first-out register having multiple address input ports and capable of storing a plurality of addresses. Address loading operations are over-lapped with address reading operations to speed up the rate at which addresses may be stored in and retrieved from the register. When the register is full of addresses it provides an indication which permits: the addresses already stored in the register to be read out and stored in an external memory, then additional addresses to be stored in the register, and subsequently the addresses transferred to the memory for storage to be retransferred to the buffer address register for read out.
摘要翻译： 一个具有多个地址输入端口并且能够存储多个地址的先进先出寄存器。 地址加载操作与地址读取操作重叠，以加快地址可以从寄存器存储和检索的速率。 当寄存器充满地址时，它提供一个指示，允许：已经存储在寄存器中的地址被读出并存储在外部存储器中，然后存储在寄存器中的附加地址，以及随后传送到存储器的地址 用于存储重新发送到缓冲地址寄存器以进行读出。
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4.发明授权
公开(公告)号：US5136500A
公开(公告)日：1992-08-04
申请号：US366225
申请日：1989-06-12
IPC分类号： G06F13/16 , G06F15/167
CPC分类号： G06F15/167 , G06F13/1663
摘要： A memory controller in which a number of local memories are primarily dedicated to the shared use of a number of local processors of a data processing system to increase the efficiency of use of both the processors and memories. A controller is associated with each local memory to control connection of any one of the local processors to its associated local memory. A local processor can also be connected via a controller and an adapter circuit connected to the controller to a system bus to obtain access to circuits connected thereto. In addition, a system processor connected to the system bus may also be connected to any particular one of the local memories via its associated controller and adapter connected thereto to load data or programs into the local memory for use by the local processors, and to read out the results of previous processing done by the local processors.
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公开(公告)号：US4935737A
公开(公告)日：1990-06-19
申请号：US927632
申请日：1986-11-05
IPC分类号： G06F7/76
CPC分类号： G06F7/76
摘要： A data selection matrix is disclosed which uses a plurality of programmed array logic (PAL) units having input thereto portions of binary words from a plurality of sources, the PALs being responsive to control words also input thereto to jointly select one of said sources of binary words and to select the arrangement of the portions of the binary words being input thereto from the selected source of binary words.
摘要翻译： 公开了一种数据选择矩阵，其使用多个编程的阵列逻辑（PAL）单元，其具有从多个源输入二进制字的部分，PAL响应于也输入到其的控制字来共同选择所述二进制源之一 并且从所选择的二进制字源中选择从其输入的二进制字的部分的排列。
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公开(公告)号：US4775929A
公开(公告)日：1988-10-04
申请号：US917940
申请日：1986-10-14
CPC分类号： G06F13/4217
摘要： What is disclosed is a time partitioned bus arrangement for use in a computer system wherein different circuits therein are interconnected by a plurality of busses and operation is such that information to be processed can be read out of one circuit, processed in some manner in another circuit, and the processed information be stored in the same or another circuit all within one cycle of a system clock in the computer system, and without the need for bus control circuits and bus interfaces in the circuitry connected to the busses. Some of the circuits have their input/output connected to only a single one of the busses, while other circuits have their input connected to one bus and their output connected to a different bus, and yet other circuits have either their input or output connected to one of the busses and their other input/output connected to circuitry external to the bus arrangement. Some of the processor circuits have a control lead input that is energized by the clock signal output from the system clock so that they accept information from one bus to which their input is connected during a first polarity portion of a clock cycle and return either unprocessed or processed information to another bus during a second polarity portion of a clock cycle.
摘要翻译： 所公开的是用于计算机系统中的时间分配总线布置，其中其中不同的电路通过多个总线互连，并且操作使得可以从一个电路中读出要处理的信息，以某种方式在另一个电路中进行处理 并且处理的信息在计算机系统中的系统时钟的一个周期内被存储在相同或另一个电路中，并且不需要连接到总线的电路中的总线控制电路和总线接口。 一些电路的输入/输出仅连接到总线中的单个总线，而其他电路的输入连接到一个总线，其输出连接到不同的总线，而其他电路的输入或输出连接到 总线中的一个和其他输入/输出连接到总线布置外部的电路。 一些处理器电路具有由从系统时钟输出的时钟信号激励的控制引线输入，使得它们在时钟周期的第一极性部分期间接收来自其输入连接到的一个总线的信息，并返回未处理的或 在时钟周期的第二极性部分处理信息到另一个总线。
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7.发明授权Delayed acknowledgement in an asymmetric timer based LAN communications protocol 失效在基于非对称定时器的局域网通信协议中进行延迟确认
公开(公告)号：US5528605A
公开(公告)日：1996-06-18
申请号：US328946
申请日：1994-10-25
CPC分类号： H04L1/1635 , H04L1/1835 , H04L1/1848 , H04L1/1854 , H04L1/1874 , H04L1/188 , H04L1/1887 , H04L29/06 , H04L69/324
摘要： A computer communications system has a controller for controlling a master with a circuit timer, the circuit timer is capable of aggregating data produced during a circuit timer interval into a single master message, and the data is produced by a plurality of users, where each user is capable of establishing a plurality of sessions. There is a communication pathway, responsive to expiration of the circuit timer interval, for sending the aggregated data to a slave. Also there is a acknowledgement circuit for the slave to send an acknowledge message to the master upon expiration of a delay ACK time interval, the delay ACK time interval is greater than the circuit timer interval, and the circuit timer is capable of initiating sending of a plurality of master messages during one delay ACK time interval. Further, there is a delay acknowledgement circuit, responsive to receipt of the plurality of master messages, for the slave to acknowledge the plurality of master messages in one acknowledge message, and each user and each session being acknowledged by the one acknowledge message.
摘要翻译： 计算机通信系统具有控制器，用于利用电路定时器控制主机，电路定时器能够将在电路定时器间隔期间产生的数据聚合成单个主消息，并且数据由多个用户产生，其中每个用户 能够建立多个会话。 响应于电路定时器间隔的到期，存在用于将聚合数据发送到从设备的通信路径。 还有一个确认电路，用于从机在延迟ACK时间间隔到期时向主设备发送确认消息，延迟ACK时间间隔大于电路定时器间隔，并且电路定时器能够启动发送 在一个延迟ACK时间间隔期间的多个主消息。 此外，存在响应于接收到多个主消息的延迟确认电路，用于从机在一个确认消息中确认多个主消息，并且每个用户和每个会话由一个确认消息确认。
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