公开(公告)号：US4320455A

公开(公告)日：1982-03-16

申请号：US100028

申请日：1979-12-03

申请人： William E. Woods ,  Philip E. Stanley ,  Thomas S. Hirsch

发明人： William E. Woods ,  Philip E. Stanley ,  Thomas S. Hirsch

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F9/36

CPC分类号： G06F9/4881 ,  G06F9/546

摘要： One or more queue structures in a data processing system may include a threaded list of frames which are enqueued or dequeued from the list in accordance with four instructions wherein each list is tied to a so-called lock or control frame with synchronization for multiple processing units. Multiple lock frames and accordingly multiple lists of frames may be coupled in the system for the purpose of accomplishing the various tasks necessary.

摘要翻译： 数据处理系统中的一个或多个队列结构可以包括根据四个指令从列表排队或出队的帧的线程列表，其中每个列表被绑定到所谓的锁定或控制帧，具有多个处理单元的同步 。 多个锁帧和相应的多个帧列表可以耦合在系统中以实现所需的各种任务。

公开(公告)号：US5515525A

公开(公告)日：1996-05-07

申请号：US128391

申请日：1993-09-28

申请人： Marek Grynberg ,  Dennis R. Flynn ,  Thomas S. Hirsch ,  Mary E. Tovell ,  William E. Woods

发明人： Marek Grynberg ,  Dennis R. Flynn ,  Thomas S. Hirsch ,  Mary E. Tovell ,  William E. Woods

IPC分类号： G06F9/455 ,  G06F12/10 ,  G06F15/00

CPC分类号： G06F9/45537 ,  G06F12/109

摘要： A memory translation mechanism and method executing in a second system to perform first system memory operations for first system executive and user tasks executing on the second system which includes a second system memory organized as a plurality of memory segments, wherein first memory segments are designated to correspond to system memory areas and second memory segments are designated to correspond to user memory areas, and wherein each memory segment corresponds to a combination of a type of first system task and a type of a first system memory area. An interpreter maps by reading an identification of the type of the task corresponding to the first system virtual address from the task type memory and the area type value from the first system virtual address and determining a memory segment corresponding to the type of the first system task and the type of first system area referenced by the first system virtual address. The interpreter maps the identified segment to a memory pool identifier wherein each memory pool identifier corresponds to a task. The second system includes a plurality of pseudo device drivers corresponding to first system input/output devices. Each pseudo device driver includes a segment mapping mechanism which includes a segment pool for storing entries relating memory pool identifiers and providing a corresponding base address identifying the location of the corresponding memory segment in the second system memory.

摘要翻译： 一种在第二系统中执行的存储器转换机制和方法，用于对第二系统执行第一系统执行和用户任务执行第一系统存储器操作，所述第二系统执行和用户任务包括被组织为多个存储器段的第二系统存储器，其中第一存储器段被指定为 对应于系统存储器区域，并且第二存储器段被指定为对应于用户存储区域，并且其中每个存储器段对应于第一系统任务的类型和第一系统存储器区域的类型的组合。 解释器通过从任务类型存储器读取对应于第一系统虚拟地址的任务的类型的标识和来自第一系统虚拟地址的区域类型值来映射，并且确定对应于第一系统任务的类型的存储器段 以及由第一个系统虚拟地址引用的第一个系统区域的类型。 解释器将所识别的片段映射到存储器池标识符，其中每个存储器池标识符对应于任务。 第二系统包括对应于第一系统输入/输出装置的多个伪装置驱动器。 每个伪设备驱动器包括段映射机制，其包括用于存储与存储器池标识符相关的条目的段池，并且提供标识第二系统存储器中对应的存储器段的位置的相应基地址。

公开(公告)号：US5027271A

公开(公告)日：1991-06-25

申请号：US136056

申请日：1987-12-21

申请人： John L. Curley ,  Thomas S. Hirsch ,  David A. Wurz

发明人： John L. Curley ,  Thomas S. Hirsch ,  David A. Wurz

IPC分类号： G06F9/48 ,  G06F9/50 ,  G06F15/16 ,  G06F15/167 ,  G06F15/177

CPC分类号： G06F9/4843 ,  G06F15/161 ,  G06F9/468 ,  G06F9/5061

摘要： In a data processing system having a plurality of non-homogeneous central processing units, apparatus is disclosed that permits a central processing unit not having mechanisms for protection of the allocation of resources to be coupled to the data processing system while preserving a peer relationship among the central processing units. The protection apparatus is interposed between the coupled central processing unit and the system bus and reviews each access to data processing system resources to insure that the accessed system resource is available to the associated data processing system. In addition, the apparatus permits initialization procedures without interprocessor conflict, provides status information from the coupled central processing unit to a requesting central processing unit and permits selected control signals to be applied to the coupled central processing unit.

公开(公告)号：US5491790A

公开(公告)日：1996-02-13

申请号：US231856

申请日：1994-04-22

申请人： James W. Keeley ,  Richard A. Lemay ,  Chester M. Nibby, Jr. ,  Keith L. Petry ,  Thomas S. Hirsch

发明人： James W. Keeley ,  Richard A. Lemay ,  Chester M. Nibby, Jr. ,  Keith L. Petry ,  Thomas S. Hirsch

IPC分类号： G06F1/00 ,  G06F9/06 ,  G06F9/445 ,  G06F11/22 ,  G06F11/267

CPC分类号： G06F11/2236 ,  G06F11/22 ,  G06F9/4403

摘要： A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor's boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus. Following loading of the peer processor operating system, the EEPROM control circuits, in response to commands from the system bus, enable the microprocessor to address the second region for executing boot routines for loading its operating system.

摘要翻译： 除了其他单元之外，处理单元与对等处理器，主存储器共同地耦合到系统总线，并且包括紧密耦合到也可从这样的总线访问的本地存储器的微处理器。 处理单元还包括可寻址的电可擦除可编程只读存储器（EEPROM）单元，其耦合到微处理器和系统总线。 EEPROM单元存储在第一和第二分离区域中，两者分别占据通常分配用于存储微处理器引导代码，车载诊断（OBD）例程和操作系统引导例程的相同地址空间。 EEPROM控制电路在上电时，使EEPROM单元处理第一个区域以执行OBD例程，以验证处理单元是否正常工作，包括正确向连接到系统总线的单元发出命令的能力。 在加载对等处理器操作系统之后，响应于来自系统总线的命令，EEPROM控制电路使得微处理器能够寻址用于执行用于加载其操作系统的引导例程的第二区域。

公开(公告)号：US5664098A

公开(公告)日：1997-09-02

申请号：US311655

申请日：1994-09-23

申请人： Richard S. Bianchi ,  Thomas S. Hirsch ,  Ron B. Perry

发明人： Richard S. Bianchi ,  Thomas S. Hirsch ,  Ron B. Perry

IPC分类号： G06F1/00 ,  G06F9/455 ,  G06F9/46 ,  G06F13/10 ,  G06F21/00 ,  G06F11/00 ,  H04L9/00

CPC分类号： G06F9/45537 ,  G06F13/10 ,  G06F13/105 ,  G06F21/31 ,  G06F21/6281 ,  G06F2221/2105

摘要： A host data processing system which includes a plurality of input/output devices operates under the control of an enhanced version of the UNIX operating system. The host system includes an emulator which runs as an application process for executing user emulated system (ES) application programs. The emulator includes a number of emulated system executive service components operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server facilities operating in the host memory. The ES executive service components are extended to accommodate a number of dual decor commands and functions which make host system facilities directly available to ES application programs by concurrent execution of program operations within both the emulator and host system environments. The EMCU includes mechanisms for performing an initial level security validation operation which allows subsequent trusted verification of user identity when dual decor commands or functions are invoked. The server facilities include mechanisms for performing a two-step security validation process for ensuring security relative to preventing both unauthorized user access and compromises in user data through improper use of dual decor commands or functions.

摘要翻译： 包括多个输入/输出设备的主机数据处理系统在UNIX操作系统的增强版本的控制下操作。 主机系统包括作为执行用户仿真系统（ES）应用程序的应用程序运行的仿真器。 仿真器包括在共享存储器中操作的多个模拟系统执行服务组件和解释器，仿真器监视器呼叫单元（EMCU）以及在主机存储器中操作的多个服务器设备。 扩展ES执行服务组件，以适应许多双重装配命令和功能，使主机系统功能可直接通过模拟器和主机系统环境中的程序操作同时执行ES应用程序。 EMCU包括用于执行初始级别安全验证操作的机制，其允许在调用双装饰命令或功能时随后对用户身份的可信验证。 服务器设备包括用于执行两步安全验证过程的机制，以确保相对于通过不适当地使用双装饰命令或功能来防止未经授权的用户访问和危害用户数据的安全性。

公开(公告)号：US5230065A

公开(公告)日：1993-07-20

申请号：US544058

申请日：1990-06-25

申请人： John L. Curley ,  Thomas S. Hirsch ,  John C. Penney ,  Ileana S. Reisch ,  Theodore R. Staplin, Jr. ,  David A. Wurz

发明人： John L. Curley ,  Thomas S. Hirsch ,  John C. Penney ,  Ileana S. Reisch ,  Theodore R. Staplin, Jr. ,  David A. Wurz

IPC分类号： G06F9/48 ,  G06F9/50 ,  G06F13/38 ,  G06F15/16

CPC分类号： G06F9/4843 ,  G06F13/387 ,  G06F15/161 ,  G06F9/5011

摘要： A data processing system is disclosed in which a plurality of central processing units have access to all the system resources, i.e., have a peer relationship. During initialization of the data processing system, all the system resources are allocated to the individual central processing units according to a preselected distribution procedure, the identification of available resources thereafter being stored in the files of the individual central processing units. During the operation of the data processing system, the resources can be reallocated by a predetermined procedure. The central processing units entering such a relationship are required to include apparatus and/or software procedures that prevent access to system resources not assigned thereto. A mail box procedure, using locations in the main memory unit permit communication between the central processing units and are used in the dynamic allocation of resources.

摘要翻译： 公开了一种数据处理系统，其中多个中央处理单元可以访问所有系统资源，即具有对等关系。 在数据处理系统的初始化期间，根据预先选择的分配过程将所有系统资源分配给各个中央处理单元，然后将可用资源的识别存储在各个中央处理单元的文件中。 在数据处理系统的操作期间，可以通过预定的过程重新分配资源。 输入这种关系的中央处理单元需要包括防止访问未分配给它的系统资源的装置和/或软件程序。 使用主存储器单元中的位置的邮箱过程允许中央处理单元之间的通信，并且用于动态分配资源。

公开(公告)号：US5548713A

公开(公告)日：1996-08-20

申请号：US272893

申请日：1994-07-08

申请人： Keith L. Petry ,  Thomas S. Hirsch ,  James W. Keeley

发明人： Keith L. Petry ,  Thomas S. Hirsch ,  James W. Keeley

IPC分类号： G06F11/22 ,  G06F11/00

CPC分类号： G06F11/2273 ,  G06F11/22

摘要： A processing unit couples to a system bus and includes a microprocessor which tightly couples to a local memory. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which couples to the microprocessor and to the system bus. The EEPROM unit stores in first and second separate regions, on-board diagnostic (OBD) routines and boot routines, respectively. The OBD routines are organized into a plurality of categories or phases. The processing unit includes a register accessible only by the microprocessor which, under the control of the OBD routines, is loaded with a number of predetermined values at the beginning of each individual OBD routine for identifying a particular phase and subphase of testing to be performed. Means coupled to the register is directly connected to display a first phase portion of the contents of the register for indicating during which phase of testing a failure occurred. The phase and subphase contents of the register are used to identify the actual test which failed. This information provides an index into a test dictionary which indicates the specific component or group of components which failed.

摘要翻译： 处理单元耦合到系统总线并且包括紧密耦合到本地存储器的微处理器。 处理单元还包括可寻址的电可擦除可编程只读存储器（EEPROM）单元，其耦合到微处理器和系统总线。 EEPROM单元分别存储在第一和第二分离区域中，车载诊断（OBD）程序和引导程序。 OBD例程被组织成多个类别或阶段。 处理单元包括只能由微处理器访问的寄存器，在OBD程序的控制下，在每个单独的OBD程序的开始处加载多个预定值，用于识别要执行的特定阶段和次级测试。 连接到寄存器的装置被直接连接以显示寄存器的内容的第一相位部分，用于指示在发生故障的测试阶段。 寄存器的相位和相位内容用于识别失败的实际测试。 该信息为测试字典提供索引，该索引指示失败的组件的特定组件或组。

公开(公告)号：US5276738A

公开(公告)日：1994-01-04

申请号：US992210

申请日：1992-12-17

申请人： Thomas S. Hirsch

发明人： Thomas S. Hirsch

IPC分类号： G06F12/14 ,  H04L9/00 ,  H04L9/02

CPC分类号： G06F12/1408 ,  H04L9/0869

摘要： A protection mechanism includes means for taking an input binary value and generating a unique key value as well as performing the reverse operation of taking a key value and generating an input binary value. The mechanism includes a scrambler which includes an array having a number of multibit container locations for storing a unique sequence of random numbers. The scrambler forms another binary value by rearranging the bits of the input binary value as a function of the random number values in addition to altering the states of such bits as a function of the random number values and the numeric bit position values of sources of the input binary bits. The resulting binary value is applied to an alphanumeric encoder which converts the binary value into a series of alphanumeric characters containing a valid key value.

摘要翻译： 保护机制包括用于获取输入二进制值并产生唯一键值的装置，以及执行取得键值并产生输入二进制值的反向操作。 该机制包括扰码器，该加扰器包括具有多个多位容器位置的阵列，用于存储唯一的随机数序列。 加扰器通过将输入二进制值的位重新排列为随机数值的函数来形成另一个二进制值，除了改变作为随机数值的函数的这样的位的状态以及源的数字位位置值 输入二进制位。 所得到的二进制值被应用于将二进制值转换为包含有效键值的一系列字母数字字符的字母数字编码器。

公开(公告)号：US4799145A

公开(公告)日：1989-01-17

申请号：US099698

申请日：1987-09-21

申请人： Gary J. Goss ,  Thomas S. Hirsch ,  Thomas O. Holtey

发明人： Gary J. Goss ,  Thomas S. Hirsch ,  Thomas O. Holtey

IPC分类号： G06F9/445 ,  G06F9/46 ,  G06F9/48 ,  G06F15/00 ,  G06F9/00

CPC分类号： G06F9/4843 ,  G06F9/4406 ,  G06F9/54

摘要： A computer system includes a first processor with main memory, an input/output processor with associated memory and an archival memory. Prior to reloading a new operating system from archival memory into the main memory, information such as timer information is stored in the input/output memory. The input/output memory continues to update the timer information until the second operating system is bootstrap loaded into the main memory. The timer and other information may then be returned to the first processor and main memory for use by the second operating system.

摘要翻译： 计算机系统包括具有主存储器的第一处理器，具有相关存储器的输入/输出处理器和档案存储器。 在将新的操作系统从归档存储器重新加载到主存储器之前，诸如定时器信息的信息被存储在输入/输出存储器中。 输入/输出存储器继续更新定时器信息，直到第二个操作系统被引导加载到主存储器中。 然后可以将定时器和其他信息返回到第一处理器和主存储器以供第二操作系统使用。

公开(公告)号：US5675771A

公开(公告)日：1997-10-07

申请号：US311649

申请日：1994-09-23

申请人： John L. Curley ,  Thomas S. Hirsch ,  James W. Stonier ,  Kin C. Yu

发明人： John L. Curley ,  Thomas S. Hirsch ,  James W. Stonier ,  Kin C. Yu

IPC分类号： G06F1/00 ,  G06F9/455 ,  G06F9/46 ,  G06F13/10 ,  G06F21/00 ,  G06F15/16

CPC分类号： G06F13/10 ,  G06F13/105 ,  G06F21/31 ,  G06F21/6281 ,  G06F9/45537 ,  G06F2221/2105

摘要： A host data processing system which includes a plurality of input/output devices operates under the control of an enhanced version of the UNIX operating system. The host system includes an emulator which runs as an application process for executing user emulated system (ES) application programs. The emulator includes a number of emulated system executive service components operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server facilities operating in the host memory. The ES executive service command handler component is extended to accommodate a number of dual decor commands which invoke host system facilities to execute terminal based commands either synchronously or asynchronously through the automatic creation of host shell mechanisms directly accessible by emulated system users. The server facilities include a network terminal driver (NTD) server for executing emulated system user terminal requests through host system drivers. Additionally, the NTD server includes mechanisms enabling a user to have direct terminal access to host facilities for executing procedures through such shell mechanisms. The mechanisms perform trusted user level validation when each dual decor command is issued and the shell mechanisms use the host access control mechanisms for checking access when the procedure is executed preventing both unauthorized user access and compromises in user data through the improper use of dual decor commands.

摘要翻译： 包括多个输入/输出设备的主机数据处理系统在UNIX操作系统的增强版本的控制下操作。 主机系统包括作为执行用户仿真系统（ES）应用程序的应用程序运行的仿真器。 仿真器包括在共享存储器中操作的多个模拟系统执行服务组件和解释器，仿真器监视器呼叫单元（EMCU）以及在主机存储器中操作的多个服务器设备。 ES执行服务命令处理程序组件被扩展以适应一些双重装饰命令，其通过自动创建由仿真系统用户直接访问的主机壳机制来同步或异步地调用主机系统设施来执行基于终端的命令。 服务器设备包括用于通过主机系统驱动程序执行仿真系统用户终端请求的网络终端驱动器（NTD）服务器。 此外，NTD服务器包括使得用户能够直接终端访问主机设施以执行通过这些机壳的过程的机制。 当执行每个双重装饰命令时，这些机制执行受信任的用户级别验证，并且当执行该过程时，shell机制使用主机访问控制机制来检查访问，以防止未经授权的用户访问并且通过不正确地使用双装饰命令来损害用户数据 。