-
公开(公告)号：US4320455A
公开(公告)日：1982-03-16
申请号：US100028
申请日：1979-12-03
CPC分类号： G06F9/4881 , G06F9/546
摘要： One or more queue structures in a data processing system may include a threaded list of frames which are enqueued or dequeued from the list in accordance with four instructions wherein each list is tied to a so-called lock or control frame with synchronization for multiple processing units. Multiple lock frames and accordingly multiple lists of frames may be coupled in the system for the purpose of accomplishing the various tasks necessary.
摘要翻译： 数据处理系统中的一个或多个队列结构可以包括根据四个指令从列表排队或出队的帧的线程列表，其中每个列表被绑定到所谓的锁定或控制帧，具有多个处理单元的同步 。 多个锁帧和相应的多个帧列表可以耦合在系统中以实现所需的各种任务。
-
公开(公告)号：US4451883A
公开(公告)日：1984-05-29
申请号：US326260
申请日：1981-12-01
CPC分类号： G06F9/30032 , G06F9/30167
摘要： A data processing system includes a memory subsystem for storing operands and instructions and a central processing unit (CPU) for manipulating the operands by executing the instructions. The CPU includes a control store for generating signals for controlling the CPU operation. Shifters made up of multiplexers shift operands between an outer bus and a write bus in response to control store signals. The multiplexers shift the operands left or right 1, 2 or 4-bit positions including open shifts and circular shifts and also perform byte position shifting and twinning.
摘要翻译： 数据处理系统包括用于存储操作数和指令的存储器子系统和用于通过执行指令来操纵操作数的中央处理单元（CPU）。 CPU包括用于产生用于控制CPU操作的信号的控制存储器。 由复用器组成的移位器响应于控制存储信号在外部总线和写入总线之间移动操作数。 多路复用器将操作数向左或向右移位1,2或4位位置，包括开位移和循环移位，并且还执行字节位移和孪生。
-
公开(公告)号：US4079451A
公开(公告)日：1978-03-14
申请号：US674698
申请日：1976-04-07
CPC分类号： G06F9/30018 , G06F12/04
摘要： A data processing system for providing word, byte or bit addressing. A word location in a memory device may be addressed based upon the contents of a base address register. Indirect addressing may be provided to another word location based upon a word index value in an index register. Effective byte or bit addressing of the addressed word is provided in response to byte and bit index values which are produced by means of the index register. An instruction word indicates the type of addressing and directs the use of different control words included in a control storage device in order to implement the desired operation.
摘要翻译： 一种用于提供字，字节或位寻址的数据处理系统。 可以基于基地址寄存器的内容来寻址存储器设备中的字位置。 可以基于索引寄存器中的单词索引值将间接寻址提供给另一单词位置。 响应于通过索引寄存器产生的字节和位索引值，提供寻址字的有效字节或位寻址。 指令字指示寻址的类型并指示使用包括在控制存储设备中的不同控制字，以便实现期望的操作。
-
公开(公告)号：US4467417A
公开(公告)日：1984-08-21
申请号：US302903
申请日：1981-09-16
CPC分类号： G06F9/30181 , G06F9/3016 , G06F9/325
摘要： A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.
摘要翻译： 公开了一种逻辑控制系统，用于将过程信息和CPU（中央处理单元）指令的流程从中央存储器系统适应到CPU，而不会因为传输延迟或定时方差而危及存储器带宽或CPU执行速度。 在指令执行期间容纳指令修改和多任务分配。
-
5.发明授权
公开(公告)号：US4349874A
公开(公告)日：1982-09-14
申请号：US140630
申请日：1980-04-15
CPC分类号： G06F12/0862 , G06F2212/6022
摘要： In a data processing system, a central processor unit requests procedural data words or non-procedural data words stored in the system memory. A control store device executes firmware instructions including a local bus field for controlling the transfer of the requested procedural data words and non-procedural data words to the central processor unit. The requested procedural data words and non-procedural data words are transferred to the central processing unit by an interfacing device including a data bus latch for receiving the procedural data words and non-procedural data words transferred from the memory, a prefetch buffer for storing up to four words, a first set of OR gate circuits for selectively transferring the procedural data words stored in the prefetch buffer to a procedural data multiplexer for assembling either a procedural data word or a procedure address, and a second set of OR gate circuits for selectively transferring either a procedural data word or non-procedural data word to the source bus or a procedural data address or non-procedural data address to the source bus for transfer to the central processor unit.
摘要翻译： 在数据处理系统中，中央处理器单元请求存储在系统存储器中的过程数据字或非程序数据字。 控制存储设备执行固件指令，其包括本地总线字段，用于控制所请求的过程数据字和非程序数据字向中央处理器单元的传送。 所请求的程序数据字和非程序数据字通过包括用于接收程序数据字的数据总线锁存器和从存储器传送的非程序数据字的接口装置传送到中央处理器，用于存储的预取缓冲器 四个字，第一组OR门电路，用于选择性地将存储在预取缓冲器中的程序数据字传送到程序数据多路复用器，用于组装程序数据字或程序地址，以及第二组OR门电路，用于选择性地 将程序数据字或非程序数据字传送到源总线或程序数据地址或非程序数据地址到源总线以传送到中央处理器单元。
-
公开(公告)号：US4047247A
公开(公告)日：1977-09-06
申请号：US674517
申请日：1976-04-07
CPC分类号： G06F9/355
摘要： A final effective address of an operand is generated in a microprogrammed data processing system by use of a base address register which may include an unindexed address, an index register which may include an index address value, an instruction register which may include an instruction word, which instruction word provides control over the addressing of a control store dependent upon the state of a selected one of a plurality of test conditions. The addressed control store word provides signals for controlling the operation of the system, including the branching between such major operations as instruction fetching, addressing, reading, writing, and execution as well as branching between minor operations which are included in the major operations.
摘要翻译： 操作数的最终有效地址在微程序数据处理系统中通过使用可包括无索引地址的基址寄存器，可包括索引地址值的索引寄存器，可包括指令字的指令寄存器， 该指令字取决于多个测试条件中所选择的一个的状态来提供对控制存储器的寻址的控制。 寻址的控制存储字提供用于控制系统操作的信号，包括在诸如指令获取，寻址，读取，写入和执行之类的主要操作之间的分支以及在主要操作中包括的次要操作之间的分支。
-
7.发明授权Microprogrammed control of extended integer and commercial instruction processor instructions through use of a data type field in a central processor unit 失效通过使用中央处理器单元中的数据类型字段对扩展整数和商业指令处理器指令进行微编程控制
公开(公告)号：US4491908A
公开(公告)日：1985-01-01
申请号：US326442
申请日：1981-12-01
CPC分类号： G06F9/30192 , G06F9/26 , G06F9/268
摘要： A data processing system includes a microprogram controlled central processing unit that executes instructions. The instruction words include a data type field for identifying the type of operand processed during the execution of the instruction. The data type field signals and a number of control signals are applied to the address terminals of a read only memory. The read only memory output signals are tested by microwords of a microprogram to branch to firmware routines to process the operand type.
摘要翻译： 数据处理系统包括执行指令的微程序控制的中央处理单元。 指令字包括用于识别在执行指令期间处理的操作数的类型的数据类型字段。 数据类型场信号和多个控制信号被施加到只读存储器的地址端子。 只读存储器输出信号由微程序的微字测试以分支到固件例程以处理操作数类型。
-
8.发明授权
公开(公告)号：US4460959A
公开(公告)日：1984-07-17
申请号：US302904
申请日：1981-09-16
CPC分类号： G06F12/0859
摘要： A logic control system comprised of a cache memory system and a transfer control logic unit is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system on a common communication bus to a CPU. The CPU and the transfer control logic unit communicate by way of the cache memory system with the common communication bus. In response to a CPU request to the central memory system, procedural information and instructions are requested by the transfer control logic unit from the cache memory system and presented to the CPU in such a manner as to avoid interruptions in CPU activity caused by information transfer delays.
摘要翻译： 公开了一种由高速缓冲存储器系统和传送控制逻辑单元组成的逻辑控制系统，用于将来自中央存储器系统的程序信息和CPU（中央处理单元）指令的流程从公共通信总线上的CPU接收到CPU。 CPU和传输控制逻辑单元通过具有公共通信总线的高速缓冲存储器系统进行通信。 响应于对中央存储器系统的CPU请求，传输控制逻辑单元从高速缓冲存储器系统请求程序信息和指令，并以这样的方式呈现给CPU，以避免由信息传输延迟引起的CPU活动中断 。
-
公开(公告)号：US4348723A
公开(公告)日：1982-09-07
申请号：US140642
申请日：1980-04-15
CPC分类号： G06F9/267
摘要： A first bank or a second bank of storage locations of a control store of a data processing system is enabled in response to one of a plurality of test signals received as parallel inputs by two multiplexer devices. Only one of the multiplexers is enabled at a given time in response to the polarity of one of the test signals selected from the inputs of the multiplexer devices.
摘要翻译： 响应于由两个多路复用器装置作为并行输入接收的多个测试信号中的一个启用数据处理系统的控制存储器的第一存储体或第二存储区域。 响应于从多路复用器装置的输入中选择的一个测试信号的极性，在给定时间只有一个复用器被使能。
-
公开(公告)号：US4467416A
公开(公告)日：1984-08-21
申请号：US302898
申请日：1981-09-16
CPC分类号： G06F9/325 , G06F9/3016
摘要： A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.
摘要翻译： 公开了一种逻辑控制系统，用于将过程信息和CPU（中央处理单元）指令的流程从中央存储器系统适应到CPU，而不会因为传输延迟或定时方差而危及存储器带宽或CPU执行速度。 在指令执行期间容纳指令修改和多任务分配。
-
-
-
-
-
-
-
-
-
搜索结果
26 条记录 (耗时 0.025 秒)
