Common-Mode Feedback Method Using a Current Starved Replica Biasing
    1.
    发明申请
    Common-Mode Feedback Method Using a Current Starved Replica Biasing 有权
    使用当前饥饿的副本偏置的共模反馈方法

    公开(公告)号:US20090189654A1

    公开(公告)日:2009-07-30

    申请号:US12019748

    申请日:2008-01-25

    IPC分类号: H03L7/06

    CPC分类号: H03L7/0895

    摘要: A method, system, and circuit design product for setting the common-mode voltage level of a charge pump to yield low duty cycle distortion from a voltage controlled oscillator (VCO). Differential charge pumps utilize common-mode feedback (CMF) networks to control the common-mode voltage level. A replica circuit of a current starved delay cell from a VCO replaces the unity gain buffering circuit within a common-mode feedback circuit. Inserting the current starved delay cell replica circuit permits adequate negative feedback compensation, while allowing a phase locked loop (PLL) to operate with a wide bandwidth. As a result of utilizing the replica circuit of a current starved delay cell from a VCO, the common-mode voltage level is optimally centered to interface with the VCO, thereby minimizing duty cycle distortion.

    摘要翻译: 一种用于设置电荷泵的共模电压电平以从压控振荡器(VCO)产生低占空比失真的方法,系统和电路设计产品。 差分电荷泵利用共模反馈(CMF)网络来控制共模电压电平。 来自VCO的当前饥饿延迟单元的复制电路替代共模反馈电路内的单位增益缓冲电路。 插入当前受饥饿的延迟单元复制电路允许充分的负反馈补偿,同时允许锁相环(PLL)以宽带宽工作。 作为利用来自VCO的当前饥饿延迟单元的复制电路的结果,共模电压电平被最佳地集中于与VCO的接口,从而最小化占空比失真。

    Single-ended to differential translator to control current starved delay cell bias
    2.
    发明授权
    Single-ended to differential translator to control current starved delay cell bias 失效
    单端到差分转换器,用于控制当前不足的延迟单元偏置

    公开(公告)号:US07750744B2

    公开(公告)日:2010-07-06

    申请号:US12019763

    申请日:2008-01-25

    IPC分类号: H03B27/00

    CPC分类号: H03L7/0995 H03L7/0891

    摘要: A method, system, and circuit device for interfacing single-ended charge pump output to differential voltage controlled oscillator (VCO) inputs to yield low duty cycle distortion from a VCO. A single-ended charge pump output is utilized to create a compliment differential voltage leg, while optimally centering the common-mode voltage level to interface to a current starved ring VCO. A replica of the VCO's current starved delay cell is implemented along with negative feedback to generate the compliment differential voltage leg. The single-ended charge pump output is coupled to a first transistor, while a second transistor is coupled to the output of an error amplifier. The error amplifier utilizes negative feedback to bias the second transistor, forcing the output of the replica circuit to equal a reference voltage.

    摘要翻译: 一种用于将单端电荷泵输出连接到差分压控振荡器(VCO)输入的方法,系统和电路装置,以产生来自VCO的低占空比失真。 使用单端电荷泵输出来产生补偿差分电压支路,同时将共模电压电平最佳地对准到当前饥饿环形VCO的接口。 VCO的当前饥饿延迟单元的副本与负反馈一起实现以产生补偿差分电压支路。 单端电荷泵输出耦合到第一晶体管,而第二晶体管耦合到误差放大器的输出端。 误差放大器利用负反馈来偏置第二晶体管,迫使复制电路的输出等于参考电压。

    Single-Ended to Differential Translator to Control Current Starved Delay Cell Bias
    3.
    发明申请
    Single-Ended to Differential Translator to Control Current Starved Delay Cell Bias 失效
    单端到差分转换器控制当前饥饿延迟单元偏差

    公开(公告)号:US20090189701A1

    公开(公告)日:2009-07-30

    申请号:US12019763

    申请日:2008-01-25

    IPC分类号: H03L7/085 H03L7/08

    CPC分类号: H03L7/0995 H03L7/0891

    摘要: A method, system, and circuit device for interfacing single-ended charge pump output to differential voltage controlled oscillator (VCO) inputs to yield low duty cycle distortion from a VCO. A single-ended charge pump output is utilized to create a compliment differential voltage leg, while optimally centering the common-mode voltage level to interface to a current starved ring VCO. A replica of the VCO's current starved delay cell is implemented along with negative feedback to generate the compliment differential voltage leg. The single-ended charge pump output is coupled to a first transistor, while a second transistor is coupled to the output of an error amplifier. The error amplifier utilizes negative feedback to bias the second transistor, forcing the output of the replica circuit to equal a reference voltage.

    摘要翻译: 一种用于将单端电荷泵输出连接到差分压控振荡器(VCO)输入的方法,系统和电路装置,以产生来自VCO的低占空比失真。 使用单端电荷泵输出来产生补偿差分电压支路,同时将共模电压电平最佳地对准到当前饥饿环形VCO的接口。 VCO的当前饥饿延迟单元的副本与负反馈一起实现以产生补偿差分电压支路。 单端电荷泵输出耦合到第一晶体管,而第二晶体管耦合到误差放大器的输出端。 误差放大器利用负反馈来偏置第二晶体管,迫使复制电路的输出等于参考电压。

    Self series terminated serial link transmitter having segmentation for amplitude, pre-emphasis, and slew rate control and voltage regulation for amplitude accuracy and high voltage protection
    4.
    发明授权
    Self series terminated serial link transmitter having segmentation for amplitude, pre-emphasis, and slew rate control and voltage regulation for amplitude accuracy and high voltage protection 有权
    自串式串行链路发射机具有用于振幅,预加重和转换速率控制的分段,以及用于振幅精度和高电压保护的电压调节

    公开(公告)号:US07307447B2

    公开(公告)日:2007-12-11

    申请号:US11263138

    申请日:2005-10-27

    IPC分类号: H03K17/16 H03B1/00

    摘要: A circuit design method and transmitter that enables flexible control of amplitude, pre-emphasis, and slew rate utilizing a design of a segmented self-series terminated (SSST) transmitter having a parallel configuration of multiple, individually controllable segments of dual pull-up and pull-down transistors. Amplitude control, slew rate control and pre-emphasis control are enabled by manipulation/selection of normal or inverted inputs for the various segments. Also provided is a mechanism for providing/maintaining accurate output across a self-series terminated (SST) transmitter by regulating the supply voltage. Regulation of the supply voltage allows compatibility with conventional serial link receiver termination voltages and protects the transmitter output devices when those voltages are larger than the normal supply for the devices.

    摘要翻译: 一种电路设计方法和发射机,其利用分段自串式终止(SSST)发射机的设计来灵活地控制振幅,预加重和转换速率,该发射机具有双重上拉的多个单独可控段的并行配置, 下拉晶体管。 幅度控制,转换速率控制和预加重控制可以通过对各个段的正常或反相输入进行操作/选择来实现。 还提供了一种用于通过调节电源电压来提供/保持跨越自串式端接(SST)发射器的精确输出的机构。 电源电压的调节允许与传统的串行链路接收器终端电压兼容,并在这些电压大于设备的正常供电时保护发射机输出设备。

    Common-mode feedback method using a current starved replica biasing
    5.
    发明授权
    Common-mode feedback method using a current starved replica biasing 有权
    共模反馈方法使用当前饥饿的副本偏置

    公开(公告)号:US07705640B2

    公开(公告)日:2010-04-27

    申请号:US12019748

    申请日:2008-01-25

    IPC分类号: H03L7/06

    CPC分类号: H03L7/0895

    摘要: A method, system, and circuit design product for setting the common-mode voltage level of a charge pump to yield low duty cycle distortion from a voltage controlled oscillator (VCO). Differential charge pumps utilize common-mode feedback (CMF) networks to control the common-mode voltage level. A replica circuit of a current starved delay cell from a VCO replaces the unity gain buffering circuit within a common-mode feedback circuit. Inserting the current starved delay cell replica circuit permits adequate negative feedback compensation, while allowing a phase locked loop (PLL) to operate with a wide bandwidth. As a result of utilizing the replica circuit of a current starved delay cell from a VCO, the common-mode voltage level is optimally centered to interface with the VCO, thereby minimizing duty cycle distortion.

    摘要翻译: 一种用于设置电荷泵的共模电压电平以从压控振荡器(VCO)产生低占空比失真的方法,系统和电路设计产品。 差分电荷泵利用共模反馈(CMF)网络来控制共模电压电平。 来自VCO的当前饥饿延迟单元的复制电路替代共模反馈电路内的单位增益缓冲电路。 插入当前受饥饿的延迟单元复制电路允许充分的负反馈补偿,同时允许锁相环(PLL)以宽带宽工作。 作为利用来自VCO的当前饥饿延迟单元的复制电路的结果,共模电压电平被最佳地集中于与VCO的接口,从而最小化占空比失真。

    Capacitive level-shifting circuits and methods for adding DC offsets to output of current-integrating amplifier
    6.
    发明授权
    Capacitive level-shifting circuits and methods for adding DC offsets to output of current-integrating amplifier 有权
    用于将电流积分放大器的输出添加DC偏置的电容电平移位电路和方法

    公开(公告)号:US08704583B2

    公开(公告)日:2014-04-22

    申请号:US13399054

    申请日:2012-02-17

    IPC分类号: H03L5/00 H03F3/45

    摘要: Capacitive level-shifting circuits and methods are provided for adding DC offsets to the output of a current-integrating amplifier. For example, a current-integrating amplifier includes an input amplifier stage and an output offset circuit. The input amplifier stage includes an input node, a first output node, and a first switch connected between the first output node and a power supply node. The output offset circuit is connected to the first output node of the input amplifier stage and to a second output node of the current-integrating amplifier. The output offset circuit includes a first series capacitor coupled between the first output node of the input amplifier stage and the second output node of the current-integrating amplifier. The output offset circuit switchably connects a bias voltage to the second output node and charges the first series capacitor to add a DC offset to the second output node of the current-integrating amplifier.

    摘要翻译: 提供电容电平移位电路和方法用于将直流偏移添加到电流积分放大器的输出。 例如,电流积分放大器包括输入放大器级和输出偏移电路。 输入放大器级包括输入节点,第一输出节点和连接在第一输出节点和电源节点之间的第一开关。 输出偏移电路连接到输入放大器级的第一输出节点和电流积分放大器的第二输出节点。 输出偏移电路包括耦合在输入放大器级的第一输出节点和电流积分放大器的第二输出节点之间的第一串联电容器。 输出偏移电路将偏置电压切换到第二输出节点并对第一串联电容器充电,以向电流积分放大器的第二输出节点添加DC偏移。

    CAPACITIVE LEVEL-SHIFTING CIRCUITS AND METHODS FOR ADDING DC OFFSETS TO OUTPUT OF CURRENT-INTEGRATING AMPLIFIER
    7.
    发明申请
    CAPACITIVE LEVEL-SHIFTING CIRCUITS AND METHODS FOR ADDING DC OFFSETS TO OUTPUT OF CURRENT-INTEGRATING AMPLIFIER 有权
    电容式电平放大电路和直流偏置电流积分放大器输出的方法

    公开(公告)号:US20130214865A1

    公开(公告)日:2013-08-22

    申请号:US13399054

    申请日:2012-02-17

    IPC分类号: H03F3/45

    摘要: Capacitive level-shifting circuits and methods are provided for adding DC offsets to the output of a current-integrating amplifier. For example, a current-integrating amplifier includes an input amplifier stage and an output offset circuit. The input amplifier stage includes an input node, a first output node, and a first switch connected between the first output node and a power supply node. The output offset circuit is connected to the first output node of the input amplifier stage and to a second output node of the current-integrating amplifier. The output offset circuit includes a first series capacitor coupled between the first output node of the input amplifier stage and the second output node of the current-integrating amplifier. The output offset circuit switchably connects a bias voltage to the second output node and charges the first series capacitor to add a DC offset to the second output node of the current-integrating amplifier.

    摘要翻译: 提供电容电平移位电路和方法用于将直流偏移添加到电流积分放大器的输出。 例如,电流积分放大器包括输入放大器级和输出偏移电路。 输入放大器级包括输入节点,第一输出节点和连接在第一输出节点和电源节点之间的第一开关。 输出偏移电路连接到输入放大器级的第一输出节点和电流积分放大器的第二输出节点。 输出偏移电路包括耦合在输入放大器级的第一输出节点和电流积分放大器的第二输出节点之间的第一串联电容器。 输出偏移电路将偏置电压切换到第二输出节点并对第一串联电容器充电,以向电流积分放大器的第二输出节点添加DC偏移。

    High speed serial link output stage having self adaptation for various impairments
    8.
    发明授权
    High speed serial link output stage having self adaptation for various impairments 失效
    具有各种损伤的自适应的高速串行链路输出级

    公开(公告)号:US07769057B2

    公开(公告)日:2010-08-03

    申请号:US12175846

    申请日:2008-07-18

    IPC分类号: H04J99/00 H04B3/00

    CPC分类号: H04L25/0292 H04L25/03885

    摘要: A high speed serial link structure and method are provided, comprising a data driver and a replica driver structure, the replica driver structure comprising a replica driver, a calibration engine and a peak level detector. The calibration engine compares a peak level detector output to a reference value and responsively performs a data driver adjustment, wherein the data driver adjustment comprises at least one of a driver biasing adjustment, a driver intermediate stage bandwidth adjustment and a driver equalization setting adjustment. In some embodiments, the calibration engine incorporates a comparator and a digital state machine; in other embodiments, it incorporates an analog operational amplifier.

    摘要翻译: 提供了一种高速串行链路结构和方法,包括数据驱动器和复制驱动器结构,复制驱动器结构包括复制驱动器,校准引擎和峰值电平检测器。 校准引擎将峰值电平检测器输出与参考值进行比较,并响应于执行数据驱动器调整,其中数据驱动器调整包括驱动器偏置调整,驱动器中间级带宽调整和驱动器均衡设置调整中的至少一个。 在一些实施例中,校准引擎包括比较器和数字状态机; 在其他实施例中,它包括模拟运算放大器。

    Systems and Methods for Producing Energy
    9.
    发明申请
    Systems and Methods for Producing Energy 审中-公开
    生产能源的系统和方法

    公开(公告)号:US20150099285A1

    公开(公告)日:2015-04-09

    申请号:US14462143

    申请日:2014-08-18

    摘要: The present invention relates to systems and methods for producing energy. Specifically, the present invention relates to systems and methods for producing energy, such as energy in the form of electricity, and fuels, such as, for example, biodiesel and/or cellulosic ethanol in a small scale energy center. Moreover, the systems and methods of the present invention provide for recovery of materials, such as in soil production and/or recycling.

    摘要翻译: 本发明涉及用于生产能量的系统和方法。 具体地,本发明涉及用于生产能量的系统和方法,例如在电力形式中的能量,以及燃料,例如在小规模能量中心的生物柴油和/或纤维素乙醇。 此外,本发明的系统和方法提供材料的回收,例如在土壤生产和/或回收中。

    Method for manufacturing a calibration device
    10.
    发明授权
    Method for manufacturing a calibration device 失效
    校准装置的制造方法

    公开(公告)号:US07698802B2

    公开(公告)日:2010-04-20

    申请号:US12028439

    申请日:2008-02-08

    IPC分类号: G01R31/28

    摘要: A method for manufacturing a calibration device for an active circuit on a chip, comprises: providing an active circuit that is capable of exhibiting a desired electrical characteristic; and providing a calibration mechanism on-chip with the active circuit. The calibration mechanism generates a control output and comprises a device under test (DUT) configured as a replica of at least one segment of the active circuit, and which generates a test output that causes finite adjustments to the control output, based on a comparison of the electrical characteristics exhibited by the DUT with a known electrical characteristic. The method further comprises: attaching to each control input terminal of the active circuit a corresponding control output from the calibration mechanism. The control output of the calibration mechanism dynamically adjusts control input applied to devices of the active circuit to force the active circuit to exhibit the desired electrical characteristic.

    摘要翻译: 一种用于制造芯片上的有源电路的校准装置的方法,包括:提供能够呈现所需电特性的有源电路; 并且提供与有源电路片上的校准机制。 所述校准机构产生控制输出,并且包括被配置为所述有源电路的至少一个段的复制品的被测器件(DUT),并且基于所述被测器件的比较,产生对所述控制输出进行有限调整的测试输出 具有已知电特性的DUT所呈现的电特性。 该方法还包括:将有源电路的每个控制输入端连接到校准机构的相应控制输出。 校准机构的控制输出动态调整施加到有源电路的器件的控制输入,以迫使有源电路呈现所需的电特性。