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25 条记录 (耗时 0.021 秒)

    Wide range and dynamically reconfigurable clock data recovery architecture
    2.
    发明授权
    Wide range and dynamically reconfigurable clock data recovery architecture 有权
    宽范围和动态可重构的时钟数据恢复架构

    公开(公告)号：US08189729B2

    公开(公告)日：2012-05-29

    申请号：US11329197

    申请日：2006-01-09

    申请人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  Wilson Wong ,  Rakesh Patel

    发明人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  Wilson Wong ,  Rakesh Patel

    IPC分类号： H04L7/00

    CPC分类号： H03L7/087 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/10 ,  H04L7/0004 ,  H04L7/033

    摘要： Wide range and dynamically reprogrammable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammed without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly.

    摘要翻译： 宽范围和动态可重新编程的CDR架构从具有广泛工作频率的串行输入数据中恢复嵌入式时钟信号。 为了支持广泛的数据速率，CDR架构包括多个操作参数。 这些参数包括各种前/后分频器设置，电荷泵电流，环路滤波器和带宽选择以及VCO齿轮。 可以在不关闭电路或PLD的情况下动态重新编程参数。 这允许CDR电路在各种标准和协议之间进行即时切换。

    Decision feedback equalization for variable input amplitude
    3.
    发明授权
    Decision feedback equalization for variable input amplitude 有权
    用于可变输入幅度的判决反馈均衡

    公开(公告)号：US08416845B1

    公开(公告)日：2013-04-09

    申请号：US11484285

    申请日：2006-07-11

    申请人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Rakesh Patel ,  Tim Tri Hoang

    发明人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Rakesh Patel ,  Tim Tri Hoang

    IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

    CPC分类号： H04L25/03057 ,  H03K5/1532

    摘要： Methods and circuits for automatic adjustment of equalization are presented that improve the quality of equalization for input signals with varying amplitudes. The methods and circuits may be used in Decision Feedback Equalization (DFE) circuits to maintain a constant equalization boost amplitude despite variations in input signal amplitude. The equalization circuitry measures the amplitude of the equalization input signal and computes tap coefficients to maintain a desired level of boost amplitude. Tap coefficients may be automatically adjusted by the equalization circuitry.

    摘要翻译： 提出了用于自动调整均衡的方法和电路，其提高具有变化幅度的输入信号的均衡质量。 方法和电路可以用于判决反馈均衡（DFE）电路中，以维持恒定的均衡提升幅度，尽管输入信号幅度有变化。 均衡电路测量均衡输入信号的幅度并计算抽头系数以维持期望的升压幅度。 抽头系数可以由均衡电路自动调整。

    Half-rate DFE with duplicate path for high data-rate operation
    4.
    发明授权
    Half-rate DFE with duplicate path for high data-rate operation 有权
    具有高数据速率操作的重复路径的半速率DFE

    公开(公告)号：US07782935B1

    公开(公告)日：2010-08-24

    申请号：US11514490

    申请日：2006-08-31

    申请人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Tin H. Lai

    发明人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Tin H. Lai

    IPC分类号： H03H7/30

    CPC分类号： H03H11/26 ,  H04L25/03878 ,  H04L2025/0349

    摘要： Methods and circuits are presented for providing equalization, including decision feedback equalization (DFE), to high data-rate signals. Half-rate delay-chain circuitry produces delayed samples of an input signal using two or more delay-chain circuits operating at a fraction of the input signal data-rate. Two delay-chain circuits operating at one-half the input signal data-rate may be used. More generally, n delay-chain circuits operating at 1/n the input signal data-rate may be used. Multiplexer circuitry combines the outputs of the delay-chain circuits to produce an output signal including samples of the input signal at the input signal data-rate. Duplicate path DFE circuitry includes two paths used to provide DFE equalization while reducing the load of the DFE circuitry on the circuitry that precedes it. A first path produces delayed samples of a DFE signal, while a second path produces the DFE output signal from the delayed samples.

    摘要翻译： 提出了用于向高数据速率信号提供均衡的方法和电路，包括判决反馈均衡（DFE）。 半速率延迟链电路使用以输入信号数据速率的一小部分工作的两个或多个延迟链电路产生输入信号的延迟采样。 可以使用以输入信号数据速率的一半工作的两个延迟链电路。 更一般地，可以使用以1 / n输入信号数据速率工作的n个延迟链电路。 多路复用器电路组合延迟链电路的输出以产生包括输入信号数据速率的输入信号样本的输出信号。 重复路径DFE电路包括用于提供DFE均衡的两个路径，同时减少DFE电路之前的电路上的DFE电路的负载。 第一路径产生DFE信号的延迟采样，而第二路径产生来自延迟采样的DFE输出信号。

    High-speed data reception circuitry and methods
    6.
    发明授权
    High-speed data reception circuitry and methods 有权
    高速数据接收电路和方法

    公开(公告)号：US08743943B2

    公开(公告)日：2014-06-03

    申请号：US11192539

    申请日：2005-07-28

    申请人： Sergey Yuryevich Shumarayev ,  Wilson Wong ,  Rakesh Patel

    发明人： Sergey Yuryevich Shumarayev ,  Wilson Wong ,  Rakesh Patel

    IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

    CPC分类号： H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03573

    摘要： Equalization circuitry for receiving a digital data signal includes both feed-forward equalizer (“FFE”) circuitry and decision-feedback equalizer (“DFE”) circuitry. The FFE circuitry may be used to give the DFE circuitry a signal that is at least minimally adequate for proper start-up of the DFE circuitry. Thereafter, more of the burden of the equalization task may be shifted from the FFE circuitry to the DFE circuitry.

    摘要翻译： 用于接收数字数据信号的均衡电路包括前馈均衡器（“FFE”）电路和判决反馈均衡器（“DFE”）电路。 FFE电路可以用于给DFE电路提供至少最不足以适当启动DFE电路的信号。 此后，均衡任务的更多负担可能从FFE电路转移到DFE电路。

    High-speed serial data receiver architecture
    7.
    发明授权
    High-speed serial data receiver architecture 有权
    高速串行数据接收机架构

    公开(公告)号：US07702011B2

    公开(公告)日：2010-04-20

    申请号：US11361192

    申请日：2006-02-23

    申请人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Wilson Wong ,  Rakesh Patel

    发明人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Wilson Wong ,  Rakesh Patel

    IPC分类号： H03H7/30

    CPC分类号： H04L1/243 ,  H04L25/03878

    摘要： Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.

    摘要翻译： 用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。 其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。 例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。 接收器电路的控制的各个方面可以是可编程的。

    Receiver equalizer circuitry having wide data rate and input common mode voltage ranges
    8.
    发明授权
    Receiver equalizer circuitry having wide data rate and input common mode voltage ranges 有权
    接收机均衡器电路具有宽数据速率和输入共模电压范围

    公开(公告)号：US08222967B1

    公开(公告)日：2012-07-17

    申请号：US12644128

    申请日：2009-12-22

    申请人： Sangeeta Raman ,  Tim Tri Hoang ,  Sergey Yuryevich Shumarayev

    发明人： Sangeeta Raman ,  Tim Tri Hoang ,  Sergey Yuryevich Shumarayev

    IPC分类号： H03H7/30 ,  H03F3/45

    CPC分类号： H03F3/45192 ,  H03F3/193 ,  H03F3/45197 ,  H03F3/45475 ,  H03F3/72 ,  H03F2200/405 ,  H03F2203/45488 ,  H03F2203/45494 ,  H03F2203/45686 ,  H03F2203/7236 ,  H03H11/1213 ,  H03H11/48

    摘要： Equalizer circuitry on an integrated circuit (“IC”) includes a plurality of NMOS equalizer stages connected in series. Each NMOS stage may include folded active inductor circuitry. Each NMOS stage may also include various circuit elements having controllably variable circuit parameters so that the equalizer can be controllably adapted to perform for any of a wide range of high-speed serial data signal bit rates and other variations of communication protocols and/or communication conditions. For example, each NMOS stage may be programmable to control at least one of bandwidth and power consumption of the equalizer circuitry. The equalizer may also have a first PMOS stage that can be used instead of the first NMOS stage in cases in which the voltage of the incoming signal to be equalized is too low for an initial NMOS stage.

    摘要翻译： 集成电路（“IC”）上的均衡器电路包括串联连接的多个NMOS均衡器级。 每个NMOS级可包括折叠的有源电感电路。 每个NMOS级还可以包括具有可控制的可变电路参数的各种电路元件，使得均衡器可被可控地适用于执行宽范围的高速串行数据信号比特率和通信协议和/或通信条件的其它变化 。 例如，每个NMOS级可以是可编程的，以控制均衡器电路的带宽和功耗中的至少一个。 在均衡的输入信号的电压对于初始NMOS级来说太低的情况下，均衡器也可以具有第一PMOS级，而不用第一NMOS级。

    Clock circuitry for programmable logic devices
    10.
    发明授权
    Clock circuitry for programmable logic devices 有权
    可编程逻辑器件的时钟电路

    公开(公告)号：US07276936B1

    公开(公告)日：2007-10-02

    申请号：US11239702

    申请日：2005-09-29

    申请人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  In Whan Kim ,  Thungoc Tran

    发明人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  In Whan Kim ,  Thungoc Tran

    IPC分类号： H03K19/00

    CPC分类号： H03K19/1774 ,  H03K19/17744

    摘要： A programmable logic device includes high-speed serial interface (“HSSI”) circuitry that employs one or more clock signals. In addition to use of these clock signals in the HSSI circuitry, circuitry is provided for allowing at least one of these signals to be distributed throughout the PLD core circuitry, e.g., for use as an additional clock signal in the PLD core. Clock distribution is preferably done in a low-skew way.

    摘要翻译： 可编程逻辑器件包括采用一个或多个时钟信号的高速串行接口（“HSSI”）电路。 除了在HSSI电路中使用这些时钟信号之外，提供电路以允许这些信号中的至少一个分布在整个PLD核心电路中，例如用作PLD核心中的附加时钟信号。 时钟分布优选以低偏斜方式进行。