公开(公告)号：US20230282279A1

公开(公告)日：2023-09-07

申请号：US17683356

申请日：2022-03-01

Applicant: Winbond Electronics Corp.

Inventor： Frederick Chen ,  Ping-Kun Wang ,  Chia-Hung Lin ,  Jun-Yao Huang

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0007 ,  G11C2013/0045

Abstract: A filament forming method includes: performing first stage to apply first bias including gate and drain voltages to a resistive memory unit plural times until read current reaches first saturating state, latching read current in first saturating state as saturating read current, determining whether increasing rate of saturating read current is less than first threshold value; when increasing rate of saturating read current is not less than first threshold value, performing second stage to apply second bias, by increasing gate voltage and decreasing drain voltage, to the resistive memory unit plural times until read current reaches second saturating state, latching read current in second saturating state as saturating read current and determining whether increasing rate of saturating read current is less than first threshold value; finishing the method when increasing rate of saturating read current is less than first threshold value and saturating read current reaches target current value.

公开(公告)号：US11972799B2

公开(公告)日：2024-04-30

申请号：US17683356

申请日：2022-03-01

Applicant: Winbond Electronics Corp.

Inventor： Frederick Chen ,  Ping-Kun Wang ,  Chia-Hung Lin ,  Jun-Yao Huang

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0007 ,  G11C2013/0045

Abstract: A filament forming method includes: performing first stage to apply first bias including gate and drain voltages to a resistive memory unit plural times until read current reaches first saturating state, latching read current in first saturating state as saturating read current, determining whether rate of increase of saturating read current is less than first threshold value; when rate of increase of saturating read current is not less than first threshold value, performing second stage to apply second bias, by increasing gate voltage and decreasing drain voltage, to the resistive memory unit plural times until read current reaches second saturating state, latching read current in second saturating state as saturating read current and determining whether rate of increase of saturating read current is less than first threshold value; finishing the method when rate of increase of saturating read current is less than first threshold value and saturating read current reaches target current value.

公开(公告)号：US12237017B2

公开(公告)日：2025-02-25

申请号：US18072723

申请日：2022-12-01

Applicant: Winbond Electronics Corp.

Inventor： Lung-Chi Cheng ,  Ying-Shan Kuo ,  Jun-Yao Huang ,  Ju-Chieh Cheng ,  Yu-Cheng Chuang

IPC: G11C16/34 ,  G11C16/16

Abstract: A block erase method for a flash memory is provided. The block erase method is to perform block erase on a block with a predetermined block size. The block erase method includes: performing an erase verification on bytes byte-by-byte in the block when performing the block erase; checking an erase step of the byte when the byte does not pass the erase verification; when the erase step of the byte exceeds a predetermined threshold value, performing the block erase with a partitioned block smaller than the predetermined block size, and returning to an erase verification stage to perform the erase verification; and when the erase step of the bytes does not exceed the predetermined threshold value, continuing to perform the block erase with the predetermined block size, and returning to the erasure verification stage to continue to perform the erase verification.

公开(公告)号：US20240087644A1

公开(公告)日：2024-03-14

申请号：US18457377

申请日：2023-08-29

Applicant: Winbond Electronics Corp.

Inventor： I-Hsien Tseng ,  Lung-Chi Cheng ,  Ju-Chieh Cheng ,  Jun-Yao Huang ,  Ping-Kun Wang

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C2013/0083

Abstract: A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.

公开(公告)号：US20230274782A1

公开(公告)日：2023-08-31

申请号：US18072723

申请日：2022-12-01

Applicant: Winbond Electronics Corp.

Inventor： Lung-Chi Cheng ,  Ying-Shan Kuo ,  Jun-Yao Huang ,  Ju-Chieh Cheng ,  Yu-Cheng Chuang

IPC: G11C16/16 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/3445 ,  G11C16/3431

Abstract: A block erase method for a flash memory is provided. The block erase method is to perform block erase on a block with a predetermined block size. The block erase method includes: performing an erase verification on bytes byte-by-byte in the block when performing the block erase; checking an erase step of the byte when the byte does not pass the erase verification; when the erase step of the byte exceeds a predetermined threshold value, performing the block erase with a partitioned block smaller than the predetermined block size, and returning to an erase verification stage to perform the erase verification; and when the erase step of the bytes does not exceed the predetermined threshold value, continuing to perform the block erase with the predetermined block size, and returning to the erasure verification stage to continue to perform the erase verification.