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公开(公告)号：US10937492B2
公开(公告)日：2021-03-02
申请号：US16742862
申请日：2020-01-14
发明人： Norio Hattori
摘要： A semiconductor storage apparatus of high convenience, which improves utilization efficiency of a memory region, is provided. A flash memory provided in the disclosure includes a memory controller and an NAND memory device. The memory controller includes an SRAM, an RRAM, and a write/selector. The SRAM stores a conversion table that converts a logical address into a physical address. The RRAM temporarily stores a small amount of data which should be programmed. The write/selector selectively writes the to-be-programmed data into the RRAM or an NAND memory unit of the NAND memory device.
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公开(公告)号：US10908989B2
公开(公告)日：2021-02-02
申请号：US16431739
申请日：2019-06-05
发明人： Norio Hattori
摘要： Provided is a variable resistance random-access memory for suppressing degradation of performance by recovering a memory cell that fails. A variable resistance random-access memory of the disclosure includes a memory array, a row selection circuit, a column selection circuit, a controller, an error checking and correcting (ECC) circuit, an error bit flag register, and an error bit address register. The memory array includes a plurality of memory cells. The column selection circuit includes a sense amplifier and a write driver/read bias circuit. The error bit flag register stores bits for indicating presence/absence of an error bit in a write operation. The error bit address register stores an address of the error bit. The controller recovers the error bit when a predetermined event occurs.
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公开(公告)号：US20210005255A1
公开(公告)日：2021-01-07
申请号：US16460995
申请日：2019-07-02
发明人： He-Hsuan Chao , Ping-Kun Wang , Seow Fong Lim , Norio Hattori , Chien-Min Wu , Chih-Hua Hung
IPC分类号： G11C13/00
摘要： A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells.
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公开(公告)号：US20200294588A1
公开(公告)日：2020-09-17
申请号：US16742862
申请日：2020-01-14
发明人： Norio Hattori
摘要： A semiconductor storage apparatus of high convenience, which improves utilization efficiency of a memory region, is provided. A flash memory provided in the disclosure includes a memory controller and an NAND memory device. The memory controller includes an SRAM, an RRAM, and a write/selector. The SRAM stores a conversion table that converts a logical address into a physical address. The RRAM temporarily stores a small amount of data which should be programmed. The write/selector selectively writes the to-be-programmed data into the RRAM or an NAND memory unit of the NAND memory device.
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公开(公告)号：US10937495B2
公开(公告)日：2021-03-02
申请号：US16460995
申请日：2019-07-02
发明人： He-Hsuan Chao , Ping-Kun Wang , Seow Fong Lim , Norio Hattori , Chien-Min Wu , Chih-Hua Hung
摘要： A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells.
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公开(公告)号：US10366750B2
公开(公告)日：2019-07-30
申请号：US15861701
申请日：2018-01-04
发明人： Norio Hattori , Masaru Yano
摘要： A semiconductor memory device for suppressing a decrease of durability caused by erasure of a block unit or programming of a word unit is provided. A resistance change memory 100 includes a memory array 110 and a controller 120. The memory array 110 stores data by a reversible and nonvolatile variable resistance element. When erasing a selected block of the memory array 110 in response to an external erasure command, the controller 120 sets an EF flag indicating the selected block is in an erasure state without changing block data. The controller 120 further includes a reading unit. The reading unit outputs data of a selected word or data indicating the erasure based on the EF flag when reading the selected word of the memory array 110 in response to an external reading command.
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公开(公告)号：US20210096947A1
公开(公告)日：2021-04-01
申请号：US17118622
申请日：2020-12-11
发明人： Norio Hattori
摘要： Provided is a variable resistance random-access memory for suppressing degradation of performance by recovering a memory cell that fails. A variable resistance random-access memory of the disclosure includes a memory array, a row selection circuit, a column selection circuit, a controller, an error checking and correcting (ECC) circuit, an error bit flag register, and an error bit address register. The memory array includes a plurality of memory cells. The column selection circuit includes a sense amplifier and a write driver/read bias circuit. The error bit flag register stores bits for indicating presence/absence of an error bit in a write operation. The error bit address register stores an address of the error bit. The controller recovers the error bit when a predetermined event occurs.
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公开(公告)号：US20200310960A1
公开(公告)日：2020-10-01
申请号：US16742872
申请日：2020-01-14
发明人： Norio Hattori
摘要： A semiconductor memory device capable of smoothing the number of cycles of programming/erasing between blocks is provided. The semiconductor memory device includes: a memory cell array; an address translation table defining a relationship between logical address information and physical address information; an invalid block table managing the physical address information for identifying to-be-erased blocks of the blocks; a free block table managing the physical address information used for identifying erased usable blocks; an erasing element for erasing the blocks; a controller. When an erasing command and first logical address information are received from environment, the controller erases the block of the physical address information selected from the invalid block table, and rewrites the address translation table in a manner that the physical address information selected from the free block table corresponds to the first logical address information received from the external environment.
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公开(公告)号：US20180261285A1
公开(公告)日：2018-09-13
申请号：US15861701
申请日：2018-01-04
发明人： Norio Hattori , Masaru Yano
CPC分类号： G11C13/004 , G11C8/08 , G11C13/0023 , G11C13/0028 , G11C13/0033 , G11C13/0035 , G11C13/0069 , G11C13/0097 , G11C2013/0047 , H01L27/24 , H01L2924/1438
摘要： A semiconductor memory device for suppressing a decrease of durability caused by erasure of a block unit or programming of a word unit is provided. A resistance change memory 100 includes a memory array 110 and a controller 120. The memory array 110 stores data by a reversible and nonvolatile variable resistance element. When erasing a selected block of the memory array 110 in response to an external erasure command, the controller 120 sets an EF flag indicating the selected block is in an erasure state without changing block data. The controller 120 further includes a reading unit. The reading unit outputs data of a selected word or data indicating the erasure based on the EF flag when reading the selected word of the memory array 110 in response to an external reading command.
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公开(公告)号：US11494259B2
公开(公告)日：2022-11-08
申请号：US17118622
申请日：2020-12-11
发明人： Norio Hattori
摘要： Provided is a variable resistance random-access memory for suppressing degradation of performance by recovering a memory cell that fails. A variable resistance random-access memory of the disclosure includes a memory array, a row selection circuit, a column selection circuit, a controller, an error checking and correcting (ECC) circuit, an error bit flag register, and an error bit address register. The memory array includes a plurality of memory cells. The column selection circuit includes a sense amplifier and a write driver/read bias circuit. The error bit flag register stores bits for indicating presence/absence of an error bit in a write operation. The error bit address register stores an address of the error bit. The controller recovers the error bit when a predetermined event occurs.
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