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公开(公告)号：US11520526B2
公开(公告)日：2022-12-06
申请号：US17337003
申请日：2021-06-02
发明人： Ping-Kun Wang , Shao-Ching Liao , Chien-Min Wu , Chia Hua Ho , Frederick Chen , He-Hsuan Chao , Seow-Fong Lim
摘要： A write method for a resistive memory including a storage array, a control circuit and an access circuit is provided. The control circuit receives an external command to activate the access circuit to access the storage array. The write method includes determining whether the external command is ready to perform a write operation for the storage array; generating a first operation voltage group to the access circuit when the external command does not perform the write operation for the storage array; reading a count value of a block that corresponds to a write address when the external command performs the write operation for the storage array, wherein the count value indicates the number of times that the block corresponding to the write address performs the write operation; and generating a second operation voltage group to the access circuit according to the count value of the block.
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公开(公告)号：US20220069209A1
公开(公告)日：2022-03-03
申请号：US17002759
申请日：2020-08-25
发明人： Ping-Kun Wang , Chia-Wen Cheng , He-Hsuan Chao , Frederick Chen , Chang-Tsung Pai , Tzu-Yun Huang , Ming-Che Lin
摘要： A resistive memory device and a reliability enhancement method thereof are provided. The reliability enhancement method includes the following steps. A forming operation is performed on a plurality of memory cells. The formed memory cells are read to respectively obtain a plurality of formed currents. A reference current is set according to a statistic value of the formed currents. A setting operation is performed on the memory cells. A ratio between a set current of each of the memory cells and the reference current is calculated, and a physical status of each of the memory cells is judged according to the ratio. It is determined whether to perform a fix operation of each of the memory cells or not according to physical status.
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公开(公告)号：US11362272B2
公开(公告)日：2022-06-14
申请号：US17002759
申请日：2020-08-25
发明人： Ping-Kun Wang , Chia-Wen Cheng , He-Hsuan Chao , Frederick Chen , Chang-Tsung Pai , Tzu-Yun Huang , Ming-Che Lin
摘要： A resistive memory device and a reliability enhancement method thereof are provided. The reliability enhancement method includes the following steps. A forming operation is performed on a plurality of memory cells. The formed memory cells are read to respectively obtain a plurality of formed currents. A reference current is set according to a statistic value of the formed currents. A setting operation is performed on the memory cells. A ratio between a set current of each of the memory cells and the reference current is calculated, and a physical status of each of the memory cells is judged according to the ratio. It is determined whether to perform a fix operation of each of the memory cells or not according to physical status.
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公开(公告)号：US10714157B1
公开(公告)日：2020-07-14
申请号：US16551752
申请日：2019-08-27
发明人： Ming-Che Lin , He-Hsuan Chao , Ping-Kun Wang , Seow Fong Lim , Ngatik Cheung , Chia-Wen Cheng
IPC分类号： G11C7/10
摘要： A non-volatile memory and a reset method thereof are provided. The reset method includes: performing a first reset operation on a plurality of memory cells; recording a plurality of first verifying currents respectively corresponding to a plurality of first failure memory cells; performing a second reset operation on the first failure memory cells, and verifying second failure memory cells to obtain a plurality of second verifying currents; setting a first voltage modify flag according to a plurality of first ratios between the first verifying currents and the respectively corresponding second verifying currents; and adjusting a reset voltage for performing the first reset operation and the second reset operation according to the first voltage modify flag.
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公开(公告)号：US12063796B2
公开(公告)日：2024-08-13
申请号：US17960121
申请日：2022-10-04
发明人： Chia-Wen Cheng , Ping-Kun Wang , Yi-Hsiu Chen , He-Hsuan Chao
CPC分类号： H10B63/84 , H10B63/30 , H10N70/061 , H10N70/841
摘要： A manufacturing method is provided. The method includes steps below. Forming bottom electrodes. Blanketly forming a resistance switching layer on the bottom electrodes. Forming a first insulating material layer on the resistance switching layer. Patterning the first insulating material layer to form insulating patterns. Conformally forming a channel layer having a plurality of channel regions on the resistance switching layer and the insulating patterns, wherein the plurality of channel regions are located on the resistance switching layer and cover opposite sides of the insulating patterns. Forming a second electrode material layer on the channel layer. Patterning the second electrode material layer to form top electrodes, each of the top electrodes is located in corresponding to one of the insulating patterns and covers at least two of the plurality of channel regions.
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公开(公告)号：US11502131B2
公开(公告)日：2022-11-15
申请号：US16952085
申请日：2020-11-19
发明人： Chia-Wen Cheng , Ping-Kun Wang , Yi-Hsiu Chen , He-Hsuan Chao
摘要： A resistive random access memory (RRAM) device and a manufacturing method are provided. The RRAM device includes bottom electrodes, a resistance switching layer, insulating patterns, a channel layer and top electrodes. The resistance switching layer blanketly covers the bottom electrodes. The insulating patterns are disposed on the resistance layer and located in corresponding to locations of the bottom electrodes. The channel layer conformally covers the resistance switching layer and the insulating patterns. The channel layer has a plurality of channel regions. The channel regions are located on the resistance switching layer, and cover sidewalls of the insulating patterns. The top electrodes respectively cover at least two of the channel regions, and respectively located in corresponding to one of the insulating patterns, such that the at least two of the channel regions are located between one of the bottom electrodes and one of the top electrodes.
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公开(公告)号：US10937495B2
公开(公告)日：2021-03-02
申请号：US16460995
申请日：2019-07-02
发明人： He-Hsuan Chao , Ping-Kun Wang , Seow Fong Lim , Norio Hattori , Chien-Min Wu , Chih-Hua Hung
摘要： A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells.
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公开(公告)号：US11055021B2
公开(公告)日：2021-07-06
申请号：US16353339
申请日：2019-03-14
发明人： Ping-Kun Wang , Shao-Ching Liao , Chien-Min Wu , Chia Hua Ho , Frederick Chen , He-Hsuan Chao , Seow-Fong Lim
摘要： A resistive memory including a storage array, a storage circuit, a control circuit, a voltage generation circuit and an access circuit is provided. The storage array includes a plurality of blocks. Each block includes a plurality of memory cells. The storage circuit stores a plurality of count values. Each of the count values indicates the number of times that a corresponding block performs a write operation. The control circuit generates a control signal according to the count values when an external command is a write command. The voltage generation circuit provides an operation voltage group according to the control signal. The access circuit accesses the storage array according to the operation voltage group.
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公开(公告)号：US20210005255A1
公开(公告)日：2021-01-07
申请号：US16460995
申请日：2019-07-02
发明人： He-Hsuan Chao , Ping-Kun Wang , Seow Fong Lim , Norio Hattori , Chien-Min Wu , Chih-Hua Hung
IPC分类号： G11C13/00
摘要： A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells.
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公开(公告)号：US10770167B1
公开(公告)日：2020-09-08
申请号：US16281063
申请日：2019-02-20
发明人： Ping-Kun Wang , Ming-Che Lin , Chien-Min Wu , He-Hsuan Chao , Chih-Cheng Fu , Shao-Ching Liao
摘要： A memory storage apparatus and a forming method of a resistive memory device thereof are provided. A test forming voltage is applied to a redundant resistive memory device and a corresponding test current is read. A forming voltage applied to a main memory cell block is determined according to the test forming voltage, the test current, a forming current-voltage characteristic data and a target forming current.
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