公开(公告)号：US20170040532A1

公开(公告)日：2017-02-09

申请号：US14977664

申请日：2015-12-22

Applicant: Winbond Electronics Corp.

Inventor： Tseung-Yuen Tseng ,  Shun-Li Lan ,  Hsiang-Yu Chang ,  Chun-An Lin

IPC: H01L45/00

CPC classification number: H01L45/122 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146

Abstract: A resistive random access memory (RRAM) including a substrate, a conductive layer, a resistive switching layer, a copper-containing oxide layer, and an electron supply layer is provided. The conductive layer is disposed on the substrate. The resistive switching layer is disposed on the conductive layer. The copper-containing oxide layer is disposed on the resistive switching layer. The electron supply layer is disposed on the copper-containing oxide layer.

Abstract translation: 提供了包括基板，导电层，电阻开关层，含铜氧化物层和电子供给层的电阻随机存取存储器（RRAM）。 导电层设置在基板上。 电阻开关层设置在导电层上。 含铜氧化物层设置在电阻式开关层上。 电子供给层设置在含铜氧化物层上。

公开(公告)号：US12087619B2

公开(公告)日：2024-09-10

申请号：US18087802

申请日：2022-12-22

Applicant: Winbond Electronics Corp.

Inventor： Chi-Ching Liu ,  Yu-Ting Chen ,  Chang-Tsung Pai ,  Shun-Li Lan ,  Yen-De Lee ,  Chih-Jung Ni

IPC: H01L21/768 ,  H10B99/00

CPC classification number: H01L21/76816 ,  H10B99/00

Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.

公开(公告)号：US20230129196A1

公开(公告)日：2023-04-27

申请号：US18087802

申请日：2022-12-22

Applicant: Winbond Electronics Corp.

Inventor： Chi-Ching Liu ,  Yu-Ting Chen ,  Chang-Tsung Pai ,  Shun-Li Lan ,  Yen-De Lee ,  Chih-Jung Ni

IPC: H01L21/768 ,  H10B99/00

Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.

公开(公告)号：US11329226B2

公开(公告)日：2022-05-10

申请号：US16695774

申请日：2019-11-26

Applicant: Winbond Electronics Corp.

Inventor： Shun-Li Lan

IPC: H01L45/00

Abstract: A method of forming a memory device includes forming a first electrode; forming a resistive switching layer over the first electrode; forming a dielectric layer over the resistive switching layer; forming a first opening in the dielectric layer, wherein the first opening passes through the dielectric layer and exposes the resistive switching layer; forming a first trench in the dielectric layer, wherein the first trench is directly above the first opening; and forming a second electrode having a step shape in the first opening and the first trench.

公开(公告)号：US20210287934A1

公开(公告)日：2021-09-16

申请号：US16817572

申请日：2020-03-12

Applicant: Winbond Electronics Corp.

Inventor： Chi-Ching Liu ,  Yu-Ting Chen ,  Chang-Tsung Pai ,  Shun-Li Lan ,  Yen-De Lee ,  Chih-Jung Ni

IPC: H01L21/768 ,  H01L21/8239

Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.