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公开(公告)号：US12087619B2
公开(公告)日：2024-09-10
申请号：US18087802
申请日：2022-12-22
发明人： Chi-Ching Liu , Yu-Ting Chen , Chang-Tsung Pai , Shun-Li Lan , Yen-De Lee , Chih-Jung Ni
IPC分类号： H01L21/768 , H10B99/00
CPC分类号： H01L21/76816 , H10B99/00
摘要： A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.
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公开(公告)号：US12063875B2
公开(公告)日：2024-08-13
申请号：US18324709
申请日：2023-05-26
发明人： Yen-De Lee , Ching-Yung Wang , Chien-Hsiang Yu , Hung-Sheng Chen
CPC分类号： H10N70/063 , H10B63/80 , H10N70/066 , H10N70/841
摘要： A method for manufacturing a resistive random access memory structure is provided. The method includes providing a substrate, and the substrate includes an array region and a peripheral region. The method includes forming a first low-k dielectric layer in the peripheral region, and the first low-k dielectric layer has a dielectric constant of less than 3. The method includes forming a plurality of memory cells on the substrate and in the array region. The method includes forming a dummy memory cell at a boundary between the array region and the peripheral region. The method includes forming a gap-filling dielectric layer on the substrate. The method includes forming a plurality of first conductive plugs in the gap-filling dielectric layer, and each of the plurality of first conductive plugs is in contact with one of the plurality of memory cells.
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公开(公告)号：US10978336B2
公开(公告)日：2021-04-13
申请号：US16704152
申请日：2019-12-05
发明人： Cheng-Hui Tu , Chi-Ching Liu , Ting-Ying Shen , Yen-De Lee , Ping-Kun Wang
IPC分类号： H01L21/768
摘要： A method of manufacturing a semiconductor device includes forming a first dielectric layer and a through hole passing through the first dielectric layer over a substrate; forming a plurality of dummy contacts in the through hole; forming a plurality of first dummy wires on the plurality of dummy contacts; filling a second dielectric layer between the plurality of first dummy wires, wherein the second dielectric layer has a first air gap; removing the dummy contacts and the first dummy wires to expose the through hole, thereby forming a first wiring trench over the through hole; and forming a contact and a first wire in the through hole and the first wiring trench.
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公开(公告)号：US11737380B2
公开(公告)日：2023-08-22
申请号：US16996552
申请日：2020-08-18
发明人： Yen-De Lee , Ching-Yung Wang , Chien-Hsiang Yu , Hung-Sheng Chen
CPC分类号： H10N70/063 , H10B63/80 , H10N70/066 , H10N70/841
摘要： A resistive random access memory structure and its manufacturing method are provided. The resistive random access memory structure includes a substrate having an array region and a peripheral region. A first low-k dielectric layer located in the peripheral region has a dielectric constant of less than 3. Memory cells are located on the substrate and in the array region. A dielectric layer covers the memory cells and fills the space between adjacent memory cells in the array region, and its material layer is different from that of the first low-k dielectric layer. First conductive plugs are located in the dielectric layer and each of them is in contact with one of the memory cells. A dummy memory cell is located at the boundary between the array region and the peripheral region, and the dummy memory cell is not in contact with any one of the first conductive plugs.
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公开(公告)号：US20230129196A1
公开(公告)日：2023-04-27
申请号：US18087802
申请日：2022-12-22
发明人： Chi-Ching Liu , Yu-Ting Chen , Chang-Tsung Pai , Shun-Li Lan , Yen-De Lee , Chih-Jung Ni
IPC分类号： H01L21/768 , H10B99/00
摘要： A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.
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公开(公告)号：US20210287934A1
公开(公告)日：2021-09-16
申请号：US16817572
申请日：2020-03-12
发明人： Chi-Ching Liu , Yu-Ting Chen , Chang-Tsung Pai , Shun-Li Lan , Yen-De Lee , Chih-Jung Ni
IPC分类号： H01L21/768 , H01L21/8239
摘要： A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.
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