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    Recess gate-type semiconductor device and method of manufacturing the same
    1.
    发明授权
    Recess gate-type semiconductor device and method of manufacturing the same 失效
    嵌入式门式半导体器件及其制造方法

    公开(公告)号：US07323746B2

    公开(公告)日：2008-01-29

    申请号：US11228041

    申请日：2005-09-14

    申请人： Won-Mo Park ,  Jae-Choel Paik ,  Du-Heon Song ,  Dong-Hyun Kim ,  Chang-Sub Lee

    发明人： Won-Mo Park ,  Jae-Choel Paik ,  Du-Heon Song ,  Dong-Hyun Kim ,  Chang-Sub Lee

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L29/0692 ,  H01L29/4236

    摘要： A recess gate-type semiconductor device includes a gate electrode having a recessed portion at least partially covering a recess trench in an active region, and source/drain regions disposed in the active region that are separated by the gate electrode. The recess trench is separated from sidewalls of a device isolation region in a first direction and contacts sidewalls of the device isolation region in a second direction. The width of the recess trench of the active region in the second direction may be greater than the width of the source/drain regions in the second direction, and the recessed portion of the gate electrode may have tabs protruding in the first direction at its corners. Therefore, the semiconductor device has excellent junction leakage current and excellent refresh characteristics.

    摘要翻译： 凹槽型半导体器件包括具有至少部分地覆盖有源区中的凹槽的凹部的栅电极和设置在有源区中的由栅电极分离的源/漏区。 所述凹槽在第一方向上与器件隔离区的侧壁分离，并沿着第二方向接触器件隔离区的侧壁。 有源区在第二方向上的凹槽的宽度可以大于第二方向上的源极/漏极区的宽度，并且栅电极的凹陷部分可以具有在其角部沿第一方向突出的突出部 。 因此，半导体器件具有优异的结漏电流和优异的刷新特性。

    Recess gate-type semiconductor device and method of manufacturing the same
    2.
    发明申请
    Recess gate-type semiconductor device and method of manufacturing the same 失效
    嵌入式门式半导体器件及其制造方法

    公开(公告)号：US20060060936A1

    公开(公告)日：2006-03-23

    申请号：US11228041

    申请日：2005-09-14

    申请人： Won-Mo Park ,  Jae-Choel Paik ,  Du-Heon Song ,  Dong-Hyun Kim ,  Chang-Sub Lee

    发明人： Won-Mo Park ,  Jae-Choel Paik ,  Du-Heon Song ,  Dong-Hyun Kim ,  Chang-Sub Lee

    IPC分类号： H01L29/00

    CPC分类号： H01L29/0692 ,  H01L29/4236

    摘要： A recess gate-type semiconductor device includes a gate electrode having a recessed portion at least partially covering a recess trench in an active region, and source/drain regions disposed in the active region that are separated by the gate electrode. The recess trench is separated from sidewalls of a device isolation region in a first direction and contacts sidewalls of the device isolation region in a second direction. The width of the recess trench of the active region in the second direction may be greater than the width of the source/drain regions in the second direction, and the recessed portion of the gate electrode may have tabs protruding in the first direction at its corners. Therefore, the semiconductor device has excellent junction leakage current and excellent refresh characteristics.

    摘要翻译： 凹槽型半导体器件包括具有至少部分地覆盖有源区中的凹槽的凹部的栅电极和设置在有源区中的由栅电极分离的源/漏区。 所述凹槽在第一方向上与器件隔离区的侧壁分离，并沿着第二方向接触器件隔离区的侧壁。 有源区在第二方向上的凹槽的宽度可以大于第二方向上的源极/漏极区的宽度，并且栅电极的凹陷部分可以具有在其角部沿第一方向突出的突出部 。 因此，半导体器件具有优异的结漏电流和优异的刷新特性。

    IMAGE SENSOR HAVING 3-DIMENSIONAL TRANSFER TRANSISTOR AND ITS METHOD OF MANUFACTURE
    4.
    发明申请
    IMAGE SENSOR HAVING 3-DIMENSIONAL TRANSFER TRANSISTOR AND ITS METHOD OF MANUFACTURE 审中-公开
    具有三维传输晶体管的图像传感器及其制造方法

    公开(公告)号：US20100207170A1

    公开(公告)日：2010-08-19

    申请号：US12770957

    申请日：2010-04-30

    申请人： Kee-Hyun Paik ,  Jeong-Ho Lyu ,  Chang-Sub Lee ,  Keun-Ho Lee

    发明人： Kee-Hyun Paik ,  Jeong-Ho Lyu ,  Chang-Sub Lee ,  Keun-Ho Lee

    IPC分类号： H01L31/112

    CPC分类号： H01L27/14603 ,  H01L27/14689

    摘要： In an embodiment, an image sensor includes an isolation layer disposed in a semiconductor substrate to define a first active region and a second active region extending from the first active region. A photodiode is disposed in a portion of the first active region. A floating diffusion region is provided in the second active region at a position spaced apart from the photodiode. A transfer gate electrode is disposed on the second active region between the photodiode and the floating diffusion region. The transfer gate electrode is disposed to cover both sidewalls and an upper portion of the second active region. The transfer gate electrode has a region extending onto the first active region and overlapping the photodiode. The photodiode has a protrusion into the second active region at the portion adjacent to the transfer gate electrode. A deep n-impurity region of the photodiode extends in the protrusion.

    摘要翻译： 在一个实施例中，图像传感器包括设置在半导体衬底中以限定第一有源区和从第一有源区延伸的第二有源区的隔离层。 光电二极管设置在第一有源区的一部分中。 浮动扩散区设置在与光电二极管间隔开的位置处的第二有源区中。 传输栅电极设置在光电二极管和浮动扩散区之间的第二有源区上。 转移栅电极设置成覆盖第二有源区的两个侧壁和上部。 传输栅电极具有延伸到第一有源区上并与光电二极管重叠的区域。 光电二极管在与传输栅电极相邻的部分具有到第二有源区的突起。 光电二极管的深n杂质区域在突起中延伸。

    NON-VOLATILE MEMORY DEVICES INCLUDING DOUBLE DIFFUSED JUNCTION REGIONS AND METHODS OF FABRICATING THE SAME
    6.
    发明申请
    NON-VOLATILE MEMORY DEVICES INCLUDING DOUBLE DIFFUSED JUNCTION REGIONS AND METHODS OF FABRICATING THE SAME 有权
    非易失性存储器件，包括双重扩散接点区域及其制造方法

    公开(公告)号：US20080093648A1

    公开(公告)日：2008-04-24

    申请号：US11675372

    申请日：2007-02-15

    申请人： Dong Yean Oh ,  Jai-Hyuk Song ,  Chang-Sub Lee ,  Chang-Hyun Lee ,  Hyun-Jae Kim

    发明人： Dong Yean Oh ,  Jai-Hyuk Song ,  Chang-Sub Lee ,  Chang-Hyun Lee ,  Hyun-Jae Kim

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L27/11521 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11524

    摘要： A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.

    摘要翻译： 非易失性存储器件包括半导体衬底上的串选择栅极和接地选择栅极，以及在串选择栅极和地选择栅极之间的衬底上的多个存储单元栅极。 第一杂质区域延伸到衬底中到多个存储单元门之间的第一深度。 第二杂质区域延伸到衬底中的第二深度，该第二深度大于串选择栅极与紧邻其之间的多个存储单元栅极中的第一深度之间以及在接地选择栅极和最后一个栅极选择栅极之间的第一深度 与其紧邻的多个存储单元门。 还讨论了相关的制造方法。

    Double gate MOS transistors
    9.
    发明授权
    Double gate MOS transistors 失效
    双栅MOS晶体管

    公开(公告)号：US06940129B2

    公开(公告)日：2005-09-06

    申请号：US10715664

    申请日：2003-11-18

    申请人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

    发明人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

    CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78654

    摘要： A double gate MOS transistor includes a substrate active region defined in a semiconductor substrate and a transistor active region located over the substrate active region and overlapped with the substrate active region. At least one semiconductor pillar penetrates the transistor active region and is in contact with the substrate active region. The semiconductor pillar supports the transistor active region so that the transistor active region is spaced apart from the substrate active region. At least one bottom gate electrode fills a space between the transistor active region and the substrate active region. The bottom gate electrode is insulated from the substrate active region, the transistor active region and the semiconductor pillar. At least one top gate electrode crosses over the transistor active region and has at least one end that is in contact with a sidewall of the bottom gate electrode. The top gate electrode overlaps with the bottom gate electrode and is insulated from the transistor active region. Methods of fabricating such transistors are also provided.

    摘要翻译： 双栅MOS晶体管包括限定在半导体衬底中的衬底有源区和位于衬底有源区上方并与衬底有源区重叠的晶体管有源区。 至少一个半导体柱穿透晶体管有源区并与衬底有源区接触。 半导体柱支撑晶体管有源区，使得晶体管有源区与衬底有源区间隔开。 至少一个底栅电极填充晶体管有源区和衬底有源区之间的空间。 底栅电极与衬底有源区，晶体管有源区和半导体柱绝缘。 至少一个顶栅电极跨越晶体管有源区，并且具有与底栅电极的侧壁接触的至少一个端。 顶栅电极与底栅电极重叠并与晶体管有源区绝缘。 还提供制造这种晶体管的方法。

    NAND FLASH MEMORY DEVICE AND METHOD OF OPERATING SAME
    10.
    发明申请
    NAND FLASH MEMORY DEVICE AND METHOD OF OPERATING SAME 有权
    NAND闪存存储器件及其操作方法

    公开(公告)号：US20090257280A1

    公开(公告)日：2009-10-15

    申请号：US12405826

    申请日：2009-03-17

    申请人： Dong-Yean Oh ,  Woo-Kyung Lee ,  Jai Hyuk Song ,  Chang-Sub Lee

    发明人： Dong-Yean Oh ,  Woo-Kyung Lee ,  Jai Hyuk Song ,  Chang-Sub Lee

    IPC分类号： G11C16/06

    CPC分类号： G11C16/0483 ,  G11C16/10

    摘要： An flash memory device includes a block of NAND cell units, each NAND cell unit in the block includes n memory cell transistors MC controlled by a plurality of n wordlines, and is connected in series between a string selection transistor SST connected to a bitline and a ground selection transistor GST. While a programming voltage Vpgm is applied to a selected wordline WL , a cutoff voltage Vss is applied to a nearby unselected wordline closer to the ground selection transistor GST to isolate a first local channel Ch1 from a second local channel Ch2. As the location i of the selected wordline WL increases close to the SST, the second channel potential Vch2 tends to increase excessively, causing errors. The excessive increase of Vch2 is prevented by modifying the voltages applied to string select lines (SSL) and/or to the bit lines (BL), or the pass voltages Vpass applied to the unselected wordlines (WL location i is equal or greater than a predetermined (stored) location number x. If incremental step pulse programming (ISPP) is implemented, the applied voltages are modified only if the ISPP loop count j is equal or greater than a predetermined (stored) critical loop number y.

    摘要翻译： 闪速存储器件包括一块NAND单元单元，该块中的每个NAND单元单元包括由多个n个字线控制的n个存储单元晶体管MC，并串联连接在连接到位线的串选择晶体管SST和 接地选择晶体管GST。 当编程电压Vpgm被施加到所选字线WL时，截止电压Vss被施加到靠近接地选择晶体管GST的附近未选字线，以将第一本地信道Ch1与第二本地信道Ch2隔离。 当所选择的字线WL i的位置i增加到接近于SST时，第二通道电位Vch2会过度增加，导致错误。 通过修改施加到串选择线（SSL）和/或位线（BL）的电压或施加到未选择字线（WL ），只有当所选择的字线WL i位置i等于或大于预定（存储的）位置号码x时。 如果实现增量步进脉冲编程（ISPP），只有当ISPP循环计数j等于或大于预定（存储）的关键循环数y时，才施加电压。