公开(公告)号：US12204940B2

公开(公告)日：2025-01-21

申请号：US17648172

申请日：2022-01-17

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Yu Liu ,  Yenpang Lin ,  Stephen P. Rozum

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/54 ,  G06F12/02

Abstract: Remote kernel execution in a heterogeneous computing system can include executing, using a device processor of a device communicatively linked to a host processor, a device runtime and receiving from the host processor within a hardware submission queue of the device, a command. The command requests execution of a software kernel and specifies a descriptor stored in a region of a memory of the device shared with the host processor. In response to receiving the command, the device runtime, as executed by the device processor, invokes a runner program associated with the software kernel. The runner program can map a physical address of the descriptor to a virtual memory address corresponding to the descriptor that is usable by the software kernel. The runner program can execute the software kernel. The software kernel can access data specified by the descriptor using the virtual memory address as provided by the runner program.

公开(公告)号：US20240211302A1

公开(公告)日：2024-06-27

申请号：US18145662

申请日：2022-12-22

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Yu Liu ,  Akila Subramaniam ,  Vinod K. Kathail ,  King Chiu Tam ,  Tung Chuen Kwong ,  Pranjal Joshi ,  Soren T. Soe

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4843 ,  G06F9/5005 ,  G06F9/5061

Abstract: Dynamic provisioning of portions of a data processing array includes receiving, from an executing application, a context request. The context request specifies a requested task to be performed by a data processing array. A configuration for the data processing array is selected from a plurality of configurations for the data processing array. The selected configuration conforms with the context request and is capable of performing the requested task. A determination is made whether the selected configuration is implementable in the data processing array based, at least in part, on a space requirement of the selected configuration and a current status of the data processing array. The selected configuration is selectively implemented in the data processing array based on the determination.

公开(公告)号：US20230259627A1

公开(公告)日：2023-08-17

申请号：US17651030

申请日：2022-02-14

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Yu Liu ,  Yenpang Lin ,  Lizhi Hou ,  Cheng Zhen ,  Yidong Zhang

IPC: G06F21/57 ,  G06F21/64 ,  G06F21/71 ,  G06F13/16

CPC classification number: G06F21/572 ,  G06F21/64 ,  G06F21/71 ,  G06F13/1642 ,  G06F13/1663

Abstract: An integrated circuit can include a communication endpoint configured to maintain a communication link with a host computer, a queue configured to receive a plurality of host commands from the host computer via the communication link, and a processor configured to execute a device runtime. The processor, responsive to executing the device runtime, is configured to perform validation of the host commands read from the queue and selectively execute the host commands based on a result of the validation on a per host command basis. The host commands are executable by the processor to manage functions of the integrated circuit. The queue is implemented in a region of memory that is shared by the integrated circuit and the host computer.

公开(公告)号：US20230229497A1

公开(公告)日：2023-07-20

申请号：US17648172

申请日：2022-01-17

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Yu Liu ,  Yenpang Lin ,  Stephen P. Rozum

IPC: G06F9/50 ,  G06F9/54 ,  G06F9/30 ,  G06F12/02

CPC classification number: G06F9/5016 ,  G06F9/544 ,  G06F9/30043 ,  G06F12/0238 ,  G06F2212/7201

Abstract: Remote kernel execution in a heterogeneous computing system can include executing, using a device processor of a device communicatively linked to a host processor, a device runtime and receiving from the host processor within a hardware submission queue of the device, a command. The command requests execution of a software kernel and specifies a descriptor stored in a region of a memory of the device shared with the host processor. In response to receiving the command, the device runtime, as executed by the device processor, invokes a runner program associated with the software kernel. The runner program can map a physical address of the descriptor to a virtual memory address corresponding to the descriptor that is usable by the software kernel. The runner program can execute the software kernel. The software kernel can access data specified by the descriptor using the virtual memory address as provided by the runner program.

公开(公告)号：US11163605B1

公开(公告)日：2021-11-02

申请号：US16571776

申请日：2019-09-16

Applicant: XILINX, INC.

Inventor： Sonal Santan ,  Min Ma ,  Soren Soe ,  Cheng Zhen ,  Lizhi Hou ,  Yu Liu

IPC: G06F9/46 ,  G06F9/48

Abstract: Examples herein describe techniques for launching and executing a pipeline formed by heterogeneous processing units. A system on a chip (SoC) can include different hardware elements which form a collection of heterogeneous processing units, such as general purpose processor, programmable logic array, and specialized processors. These processing units are heterogeneous meaning their underlying hardware and techniques for processing data are different, in contrast to a system that using homogeneous processing units. In the embodiments herein, the heterogeneous processing units can be arranged into a pipeline where each stage of the pipeline is performed by one of the processing units.

公开(公告)号：US11861010B2

公开(公告)日：2024-01-02

申请号：US17651030

申请日：2022-02-14

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Yu Liu ,  Yenpang Lin ,  Lizhi Hou ,  Cheng Zhen ,  Yidong Zhang

IPC: G06F21/64 ,  G06F21/71 ,  G06F21/57 ,  G06F13/16

CPC classification number: G06F21/572 ,  G06F13/1642 ,  G06F13/1663 ,  G06F21/64 ,  G06F21/71

Abstract: An integrated circuit can include a communication endpoint configured to maintain a communication link with a host computer, a queue configured to receive a plurality of host commands from the host computer via the communication link, and a processor configured to execute a device runtime. The processor, responsive to executing the device runtime, is configured to perform validation of the host commands read from the queue and selectively execute the host commands based on a result of the validation on a per host command basis. The host commands are executable by the processor to manage functions of the integrated circuit. The queue is implemented in a region of memory that is shared by the integrated circuit and the host computer.