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公开(公告)号：US08291168B2
公开(公告)日：2012-10-16
申请号：US13342016
申请日：2011-12-31
申请人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/16
CPC分类号： G06F12/0895 , G06F1/3203 , G06F1/3275 , G06F1/3296 , G06F12/0864 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
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公开(公告)号：US07577015B2
公开(公告)日：2009-08-18
申请号：US11731184
申请日：2007-03-30
申请人： Jaume Abella , Xavier Vera , Javier Carretero Casado , Jose-Alejandro Pineiro , Antonio Gonzalez
发明人： Jaume Abella , Xavier Vera , Javier Carretero Casado , Jose-Alejandro Pineiro , Antonio Gonzalez
CPC分类号： G11C7/04 , G06F12/084 , G06F12/0893 , G06F12/0897 , G11C7/1006 , G11C7/1075
摘要： In general, in one aspect, the disclosure describes an apparatus that includes a memory device having a plurality of memory cells. An inverter is used to invert data and tag information destined for the memory device. A register is used to capture the inverted data and tag information. A write inverted value logic is used to determine when to enable writing the inverted data and tag information from the register to the memory device. When inverted data and tag information is written to a memory cell the memory cell is invalidated.
摘要翻译： 通常，在一个方面，本公开描述了一种包括具有多个存储器单元的存储器件的装置。 逆变器用于反转目的地为存储器件的数据和标签信息。 一个寄存器用于捕获反相数据和标签信息。 写反转值逻辑用于确定何时能够将反相数据和标签信息从寄存器写入存储器件。 当将反相数据和标签信息写入存储器单元时，存储器单元无效。
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公开(公告)号：US20090037783A1
公开(公告)日：2009-02-05
申请号：US11833765
申请日：2007-08-03
CPC分类号： G06F11/1008 , G06F11/1405
摘要： Embodiments of apparatuses and methods for protecting data storage structures from intermittent errors are disclosed. In one embodiment, an apparatus includes a plurality of data storage locations, execution logic, error detection logic, and control logic. The execution logic is to execute an instruction to generate a data value to store in one of the data storage locations. The error detection logic is to detect an error in the data value stored in the data storage location. The control logic is to respond to the detection of the error by causing the execution logic to re-execute the instruction to regenerate the data value to store in the data storage location, causing the error detection logic to check the data value read from the data storage location, and deactivating the data storage location if another error is detected.
摘要翻译： 公开了用于保护数据存储结构免于间歇性错误的装置和方法的实施例。 在一个实施例中，装置包括多个数据存储位置，执行逻辑，错误检测逻辑和控制逻辑。 执行逻辑是执行指令以生成数据值以存储在数据存储位置之一中。 错误检测逻辑是检测数据存储位置中存储的数据值中的错误。 控制逻辑是通过使执行逻辑重新执行用于重新生成数据值以存储在数据存储位置的指令来响应错误的检测，使得错误检测逻辑检查从数据读取的数据值 存储位置，如果检测到另一个错误，则停用数据存储位置。
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公开(公告)号：US20120110266A1
公开(公告)日：2012-05-03
申请号：US13342016
申请日：2011-12-31
申请人： Christopher Wilkerson , M. Muhammad Khellah , Vivek De , Ming Y. Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , M. Muhammad Khellah , Vivek De , Ming Y. Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F1/3203 , G06F1/3275 , G06F1/3296 , G06F12/0864 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
摘要翻译： 描述了在低电压操作期间禁用一个或多个高速缓存部分的方法和装置。 在一些实施例中，一个或多个额外的比特可以用于高速缓存的一部分，其指示高速缓存的部分是否能够在Vccmin等级或更低的值下运行。 还描述和要求保护其他实施例。
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公开(公告)号：US08103830B2
公开(公告)日：2012-01-24
申请号：US12242321
申请日：2008-09-30
申请人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/16
CPC分类号： G06F12/0895 , G06F1/3203 , G06F1/3275 , G06F1/3296 , G06F12/0864 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
摘要翻译： 描述了在低电压操作期间禁用一个或多个高速缓存部分的方法和装置。 在一些实施例中，一个或多个额外的比特可以用于高速缓存的一部分，其指示高速缓存的部分是否能够在Vccmin等级或更低的值下运行。 还描述和要求保护其他实施例。
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公开(公告)号：US20100082905A1
公开(公告)日：2010-04-01
申请号：US12242321
申请日：2008-09-30
申请人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F1/3203 , G06F1/3275 , G06F1/3296 , G06F12/0864 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
摘要翻译： 描述了在低电压操作期间禁用一个或多个高速缓存部分的方法和装置。 在一些实施例中，一个或多个额外的比特可以用于高速缓存的一部分，其指示高速缓存的部分是否能够在Vccmin等级或更低的值下运行。 还描述和要求保护其他实施例。
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公开(公告)号：US09678878B2
公开(公告)日：2017-06-13
申请号：US13652480
申请日：2012-10-16
申请人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/08 , G06F12/126 , G06F12/0864 , G06F12/0804 , G06F1/32
CPC分类号： G06F12/0864 , G06F1/3243 , G06F12/0804 , G06F2212/1028 , Y02D10/13 , Y02D10/152
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
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公开(公告)号：US20140108733A1
公开(公告)日：2014-04-17
申请号：US13652480
申请日：2012-10-16
申请人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F1/3243 , G06F12/0804 , G06F2212/1028 , Y02D10/13 , Y02D10/152
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
摘要翻译： 描述了在低电压操作期间禁用一个或多个高速缓存部分的方法和装置。 在一些实施例中，一个或多个额外的比特可以用于高速缓存的一部分，其指示高速缓存的部分是否能够在Vccmin等级或更低的值下运行。 还描述和要求保护其他实施例。
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公开(公告)号：US20100115224A1
公开(公告)日：2010-05-06
申请号：US12262070
申请日：2008-10-30
申请人： Jaume Abella , Xavier Vera , Javier Carretero Casado , Pedro Chaparro Monferrer , Antonio Gonzalez
发明人： Jaume Abella , Xavier Vera , Javier Carretero Casado , Pedro Chaparro Monferrer , Antonio Gonzalez
IPC分类号： G06F12/02
CPC分类号： G06F13/4234 , G06F12/0802 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Low supply voltage memory apparatuses are presented. In one embodiment, a memory apparatus comprises a memory and a memory controller. The memory controller includes a read controller. The read controller prevents a read operation to a memory location from being completed, for at least N clock cycles after a write operation to the memory location, where N is the number of clock cycles for the memory location to stabilize after the write operation.
摘要翻译： 提供了低电压存储装置。 在一个实施例中，存储器装置包括存储器和存储器控制器。 存储器控制器包括读控制器。 读取控制器防止对存储器位置的读取操作在对存储器位置的写入操作之后至少N个时钟周期完成，其中N是在写入操作之后存储器位置稳定的时钟周期数。
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公开(公告)号：US20080244182A1
公开(公告)日：2008-10-02
申请号：US11731184
申请日：2007-03-30
申请人： Jaume Abella , Xavier Vera , Javier Carretero Casado , Jose-Alejandro Pineiro , Antonio Gonzalez
发明人： Jaume Abella , Xavier Vera , Javier Carretero Casado , Jose-Alejandro Pineiro , Antonio Gonzalez
CPC分类号： G11C7/04 , G06F12/084 , G06F12/0893 , G06F12/0897 , G11C7/1006 , G11C7/1075
摘要： In general, in one aspect, the disclosure describes an apparatus that includes a memory device having a plurality of memory cells. An inverter is used to invert data and tag information destined for the memory device. A register is used to capture the inverted data and tag information. A write inverted value logic is used to determine when to enable writing the inverted data and tag information from the register to the memory device. When inverted data and tag information is written to a memory cell the memory cell is invalidated.
摘要翻译： 通常，在一个方面，本公开描述了一种包括具有多个存储器单元的存储器件的装置。 逆变器用于反转目的地为存储器件的数据和标签信息。 一个寄存器用于捕获反相数据和标签信息。 写反转值逻辑用于确定何时能够将反相数据和标签信息从寄存器写入存储器件。 当将反相数据和标签信息写入存储器单元时，存储器单元无效。
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