公开(公告)号：US20240063227A1

公开(公告)日：2024-02-22

申请号：US18384578

申请日：2023-10-27

Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.

Inventor： Qingjun LAI ,  Yihua ZHU ,  Yong YUAN ,  Ping AN ,  Zhaokeng CAO

IPC: H01L27/12 ,  G09G3/3225

CPC classification number: H01L27/1237 ,  H01L27/1251 ,  G09G3/3225 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2300/0465 ,  G09G2300/0814 ,  H01L27/1225 ,  H10K59/1213

Abstract: A display panel includes a base substrate, a third transistor and a fourth transistor. The third transistor and the fourth transistor are formed on the base substrate. The third transistor includes a sixth gate electrode, a third active layer, a third source electrode, and a third drain electrode. The third active layer includes an oxide semiconductor. The fourth transistor includes an eighth gate electrode, a fourth active layer, a fourth source electrode, and a fourth drain electrode. The fourth active layer includes another oxide semiconductor. Along a direction perpendicular to the base substrate, a distance between the sixth gate electrode and the third active layer is D6. A channel region of the third transistor defined by the sixth gate electrode is a sixth channel region. A length of the sixth channel region is L6. A sixth area S6=L6×D6.

公开(公告)号：US20230290288A1

公开(公告)日：2023-09-14

申请号：US18198076

申请日：2023-05-16

Applicant: Xiamen Tianma Micro-Electronics Co.,Ltd.

Inventor： Qingjun LAI ,  Yihua ZHU ,  Yong YUAN ,  Ping AN ,  Zhaokeng CAO

IPC: G09G3/20 ,  G11C19/20

CPC classification number: G09G3/20 ,  G11C19/20 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/0286 ,  G09G2310/061

Abstract: A display panel includes a shift register, a pixel circuit, and a driving circuit. The shift register includes a first control unit, a second control unit, a third control unit, and a fourth control unit. The first control unit is configured to receive an input signal and control a signal of a first node in response to a first clock signal. The second control unit is configured to receive a first voltage signal and control a signal of a second node in response to the input signal and the first clock signal. The third control unit is configured to receive the first voltage signal and a second voltage signal and control a signal of a fourth node in response to the signal of the second node and a signal of a third node.

公开(公告)号：US20230102643A1

公开(公告)日：2023-03-30

申请号：US17994581

申请日：2022-11-28

Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.

Inventor： Yong YUAN

IPC: G09G3/32

Abstract: Provided are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data write module, a drive module, a compensation module and a reset module. The drive module includes a drive transistor. The data write module is connected between a data signal input terminal and a source of the drive transistor. The compensation module is connected between a gate of the drive transistor and the drain of the drive transistor. The rest module is connected between a reset signal terminal and the drain of the drive transistor. The reset module also serves as a bias module. An operation of the pixel circuit includes a reset stage and a bias stage, during the reset stage, the reset module and the compensation module are on.

公开(公告)号：US20230093236A1

公开(公告)日：2023-03-23

申请号：US17994627

申请日：2022-11-28

Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.

Inventor： Yong YUAN

IPC: G09G3/32

Abstract: Provided are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a drive module and a data write module. The drive module is configured to provide a drive current for the light-emitting element and comprises a drive transistor. An operation of the pixel circuit includes a bias stage, in the bias stage, the data write module and the drive module are on, a compensation module is off, a data signal provides a bias signal for a drain of the drive transistor to adjust a bias state of the drive transistor.

公开(公告)号：US20220254292A1

公开(公告)日：2022-08-11

申请号：US17644627

申请日：2021-12-16

Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.

Inventor： Qingjun LAI ,  Yihua ZHU ,  Yong YUAN ,  Ping AN ,  Zhaokeng CAO

IPC: G09G3/20

Abstract: An inverter, a method for driving an inverter, a driving circuit and a display panel are provided. An inverter includes a first module; a second module; an initial signal input terminal; and a first level signal input terminal. The first module includes a first transistor, a second transistor, and a third transistor; control terminals of the first transistor and the second transistor are both electrically connected to the initial signal input terminal; a first terminal of the third transistor is electrically connected to the first level signal input terminal; a first terminal of the second transistor is electrically connected to a first terminal of the second transistor; a second terminal of the second transistor is electrically connected to a control terminal of the third transistor; the first module includes a leakage current control component at least electrically connected with the second terminal of the first transistor.

公开(公告)号：US20220208797A1

公开(公告)日：2022-06-30

申请号：US17452969

申请日：2021-10-29

Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.

Inventor： Qingjun LAI ,  Yihua ZHU ,  Yong YUAN ,  Ping AN ,  Zhaokeng CAO

IPC: H01L27/12 ,  G09G3/3225

Abstract: A display panel and a display device are provided in the present disclosure. The display panel includes a base substrate, a first transistor, a second transistor, a pixel circuit, and a drive circuit. A first active layer of the first transistor includes silicon; and a second active layer of the second transistor includes an oxide semiconductor. A length of a channel region of the first transistor is LL a distance between a first gate electrode and the first active layer is D1, and a first area S1=L1×D1; and a length of a channel region of the second transistor is L2, a distance between a second gate electrode and the second active layer is D2, and a second area S2=L2×D2, where S1

公开(公告)号：US20210104196A1

公开(公告)日：2021-04-08

申请号：US17125745

申请日：2020-12-17

Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.

Inventor： Yong YUAN

IPC: G09G3/3258 ,  G09G3/3266 ,  G09G3/3291 ,  H01L27/32

Abstract: A display panel and a driving method thereof, and a display device are provided. The display panel includes pixel circuits. Each pixel circuit includes a driving transistor, a data writing circuit, a light-emitting control circuit, a threshold compensation circuit and a bias adjustment circuit. The driving transistor includes a gate electrically connected to a first node, a first terminal electrically connected to a second node, and a second terminal electrically connected to the third node, and is configured to generate a driving current. The third node is connected to a light-emitting element through the light-emitting control circuit. The bias adjustment circuit is configured to provide a signal of a bias adjustment signal terminal to the second node under control of a signal of a first scanning signal terminal in such a manner that a bias state of the driving transistor is adjusted.

公开(公告)号：US20200279524A1

公开(公告)日：2020-09-03

申请号：US16718834

申请日：2019-12-18

Applicant: Xiamen Tianma Micro-Electronics Co.,Ltd.

Inventor： Yuheng ZHANG ,  Yong YUAN ,  Jieliang LI ,  Wanming HUANG ,  Yingteng ZHAI

IPC: G09G3/32

Abstract: Driving method for driving circuit, display panel, and display device are provided. The method includes: in a data writing stage, transmitting data signal voltage to a gate electrode of the driving transistor in response to a scan signal in a first scan signal line; in a light-emitting stage, turning on a driving path connecting the driving transistor to the light-emitting device, and making the driving transistor generate a driving current based on the voltage of the gate electrode in the driving transistor to drive the light-emitting device to emit light, in response to a light-emitting signal in a light-emitting signal line; and in a compensation stage, compensating the voltage of the gate electrode in the driving transistor by using a first power signal voltage. The light-emitting stage and the compensation stage overlap with each other, and a starting time of the compensation stage is after a starting time of the light-emitting stage.

公开(公告)号：US20170115532A1

公开(公告)日：2017-04-27

申请号：US15398328

申请日：2017-01-04

Applicant: Xiamen Tianma Micro-electronics Co., Ltd. ,  Tianma Micro-electronics Co., Ltd.

Inventor： Jieliang LI ,  Yong YUAN ,  Qi TANG

IPC: G02F1/1337 ,  G02F1/1362 ,  G02F1/1335 ,  G02F1/1368 ,  G02F1/1343

CPC classification number: G02F1/133788 ,  B32B27/281 ,  B32B2457/202 ,  C08G73/10 ,  C08G73/105 ,  C08L79/08 ,  G02B1/12 ,  G02F1/133723 ,  G02F1/134363 ,  G02F2001/133397 ,  G02F2001/133796 ,  H01L21/02118 ,  Y10T428/1023 ,  Y10T428/1055

Abstract: A display panel, a photo-alignment film, and a fabrication method of the photo-alignment film are provided. The display panel includes a first substrate, a second substrate disposed opposite to the first substrate, and a liquid crystal layer sandwiched between the first substrate and the second substrate. The first substrate includes a first photo-alignment film comprising a first photo-alignment layer and a first conductive layer that are stacked. The first photo-alignment layer is disposed close to the liquid crystal layer, and the first conductive layer is electrically connected to a conductive structure in the display panel. A resistivity of the first conductive layer is smaller than 1014 Ω·cm. The second substrate includes a second photo-alignment film disposed close to the liquid crystal layer.

公开(公告)号：US20230351940A1

公开(公告)日：2023-11-02

申请号：US18344897

申请日：2023-06-30

Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.

Inventor： Qingjun LAI ,  Yihua ZHU ,  Yong YUAN

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

Abstract: Provided are a display panel and a display device. The display panel includes a driver circuit including N stages of cascaded shift registers, where N≥2. A shift register includes a first control part and a second control part. The second control part includes a first control unit and a second control unit. The first control unit comprises a first gating unit. One terminal of the first gating unit is connected to a preset node, another terminal of the first gating unit is connected to a fourth node, and a control terminal of the first gating unit is configured to receive a fifth voltage signal. The second control unit is configured to receive at least a third voltage signal and a signal of the fourth node or receive at least a fourth voltage signal and a signal of a fifth node and generate an output signal.