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公开(公告)号：US07955952B2
公开(公告)日：2011-06-07
申请号：US12174994
申请日：2008-07-17
申请人： Xiao Hu Liu , Chih-Chao Yang , Haining Sam Yang
发明人： Xiao Hu Liu , Chih-Chao Yang , Haining Sam Yang
CPC分类号： H01L23/585 , H01L23/3171 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a continuous first stress ring proximate to a perimeter of the integrated circuit chip, respective edges of the first stress ring parallel to respective edges of the integrated circuit chip; a continuous second stress ring between the first stress ring and the perimeter of the integrated circuit chip, respective edges the second stress ring parallel to respective edges of the integrated circuit chip, the first and second stress rings having opposite internal stresses; a continuous gap between the first stress ring and the second stress ring; and a set of wiring levels from a first wiring level to a last wiring level on the substrate.
摘要翻译： 集成电路芯片和制造集成电路芯片的方法。 集成电路芯片包括：接近集成电路芯片的周边的连续的第一应力环，第一应力环的相应边缘平行于集成电路芯片的相应边缘; 所述第一应力环与所述集成电路芯片的周边之间的连续的第二应力环，所述第二应力环平行于所述集成电路芯片的相应边缘的相应边缘，所述第一和第二应力环具有相反的内应力; 第一应力环和第二应力环之间的连续间隙; 以及从基板上的第一布线电平到最后布线电平的一组布线电平。
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公开(公告)号：US20100013043A1
公开(公告)日：2010-01-21
申请号：US12174994
申请日：2008-07-17
申请人： Xiao Hu Liu , Chih-Chao Yang , Haining Sam Yang
发明人： Xiao Hu Liu , Chih-Chao Yang , Haining Sam Yang
CPC分类号： H01L23/585 , H01L23/3171 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a continuous first stress ring proximate to a perimeter of the integrated circuit chip, respective edges of the first stress ring parallel to respective edges of the integrated circuit chip; a continuous second stress ring between the first stress ring and the perimeter of the integrated circuit chip, respective edges the second stress ring parallel to respective edges of the integrated circuit chip, the first and second stress rings having opposite internal stresses; a continuous gap between the first stress ring and the second stress ring; and a set of wiring levels from a first wiring level to a last wiring level on the substrate.
摘要翻译： 集成电路芯片和制造集成电路芯片的方法。 集成电路芯片包括：接近集成电路芯片的周边的连续的第一应力环，第一应力环的相应边缘平行于集成电路芯片的相应边缘; 所述第一应力环与所述集成电路芯片的周边之间的连续的第二应力环，所述第二应力环平行于所述集成电路芯片的相应边缘的相应边缘，所述第一和第二应力环具有相反的内应力; 第一应力环和第二应力环之间的连续间隙; 以及从基板上的第一布线电平到最后布线电平的一组布线电平。
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公开(公告)号：US07790577B2
公开(公告)日：2010-09-07
申请号：US12175006
申请日：2008-07-17
申请人： Xiao Hu Liu , Chih-Chao Yang , Haining Sam Yang
发明人： Xiao Hu Liu , Chih-Chao Yang , Haining Sam Yang
IPC分类号： H01L21/00
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a set of wiring levels stacked from a first wiring level to a last wiring level; and a respective void in each wiring level of two or more wiring levels of the set wiring levels, each respective void extending in a continuous ring parallel and proximate to a perimeter of the integrated circuit chip, a void of a higher wiring level stacked directly over but not contacting a void of a lower wiring level, the respective voids forming a crack stop.
摘要翻译： 集成电路芯片和制造集成电路芯片的方法。 集成电路芯片包括：从第一布线电平堆叠到最后布线电平的一组布线电平; 以及设定布线层的两个或多个布线层次的每个布线层中的相应空隙，每个相应的空隙以连续的环平行并靠近集成电路芯片的周边延伸，直接堆叠在较高布线层上的空隙 但是不接触下部布线层的空隙，各个空隙形成裂纹停止。
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公开(公告)号：US20100012950A1
公开(公告)日：2010-01-21
申请号：US12175006
申请日：2008-07-17
申请人： Xiao Hu Liu , Chih-Chao Yang , Haining Sam Yang
发明人： Xiao Hu Liu , Chih-Chao Yang , Haining Sam Yang
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a set of wiring levels stacked from a first wiring level to a last wiring level; and a respective void in each wiring level of two or more wiring levels of the set wiring levels, each respective void extending in a continuous ring parallel and proximate to a perimeter of the integrated circuit chip, a void of a higher wiring level stacked directly over but not contacting a void of a lower wiring level, the respective voids forming a crack stop.
摘要翻译： 集成电路芯片和制造集成电路芯片的方法。 集成电路芯片包括：从第一布线电平堆叠到最后布线电平的一组布线电平; 以及设定布线层的两个或多个布线层次的每个布线层中的相应空隙，每个相应的空隙以连续的环平行并靠近集成电路芯片的周边延伸，直接堆叠在较高布线层上的空隙 但是不接触下部布线层的空隙，各个空隙形成裂纹停止。
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5.发明授权公开(公告)号：US07518191B1
公开(公告)日：2009-04-14
申请号：US12173280
申请日：2008-07-15
IPC分类号： H01L29/00
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/26586 , H01L29/665 , H01L29/6659 , H01L29/66772 , H01L29/7835 , H01L29/78618
摘要： Silicon on insulator devices having the body-tied-to-source are described. In an embodiment, a semiconductor device comprises: a gate conductor spaced above a semiconductor layer by a gate dielectric; dielectric spacers disposed laterally adjacent to sidewalls of the gate conductor; source and drain junctions laterally spaced apart by a body region in the semiconductor layer; and a conductive implant region comprising metallic species disposed in a bottom region of the semiconductor layer for electrically connecting the source junction to the body region, wherein a drain-side of the implant region is spaced apart from the body region and a source-side of the implant region contacts the body region.
摘要翻译： 描述了具有身体绑定到源的绝缘体上硅器件。 在一个实施例中，半导体器件包括：通过栅极电介质在半导体层之上间隔开的栅极导体; 电介质间隔件设置成横向邻近门导体的侧壁; 源极和漏极结，其横向间隔开半导体层中的体区; 以及导电植入区域，其包括设置在所述半导体层的底部区域中的金属物质，用于将所述源极接头与所述体区域电连接，其中所述植入区域的漏极侧与所述体区域间隔开，并且源极侧 植入区域接触身体区域。
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6.发明授权公开(公告)号：US07442614B1
公开(公告)日：2008-10-28
申请号：US12052807
申请日：2008-03-21
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/26586 , H01L29/665 , H01L29/6659 , H01L29/66772 , H01L29/7835 , H01L29/78618
摘要： Methods of fabricating silicon on insulator devices having the body-tied-to-source are described. In an embodiment, a method of forming a transistor device comprises: providing a semiconductor topography comprising a gate conductor spaced above a semiconductor layer by a gate dielectric, dielectric sidewall spacers adjacent to sidewalls of the gate conductor, and source and drain junctions laterally spaced apart by a body region in the semiconductor layer; and implanting metallic species in a bottom region of the semiconductor layer to form a conductive implant region to electrically connect the source junction to the body region.
摘要翻译： 描述了具有身体绑定到源的绝缘体上的硅的制造方法。 在一个实施例中，一种形成晶体管器件的方法包括：提供包括通过栅极电介质在半导体层之上间隔开的栅极导体的半导体形貌，与栅极导体的侧壁相邻的电介质侧壁间隔和横向间隔开的源极和漏极结 通过半导体层中的体区; 以及将所述金属物质植入所述半导体层的底部区域中以形成导电注入区域，以将所述源极结电连接到所述身体区域。
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公开(公告)号：US09620619B2
公开(公告)日：2017-04-11
申请号：US13348894
申请日：2012-01-12
申请人： Veeraraghavan S. Basker , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Veeraraghavan S. Basker , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/20 , H01L29/78 , H01L29/66 , H01L21/768 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/76897 , H01L29/66628 , H01L29/78
摘要： A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.
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公开(公告)号：US09059254B2
公开(公告)日：2015-06-16
申请号：US13604660
申请日：2012-09-06
IPC分类号： H01L21/44 , H01L21/768 , H01L21/311
CPC分类号： H01L23/528 , H01L21/31144 , H01L21/76807 , H01L21/76816 , H01L21/76831 , H01L23/5226 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.
摘要翻译： 提供了一种方法，其包括首先根据第一掩模蚀刻衬底。 第一蚀刻在衬底中形成第一深度的第一蚀刻特征。 第一蚀刻还在衬底中形成条条开口。 然后可以用填充材料填充条子开口。 可以通过去除第一掩模的一部分来形成第二掩模。 可以用第二蚀刻蚀刻由第二掩模曝光的衬底，其中第二蚀刻对填充材料是选择性的。 第二蚀刻将第一蚀刻特征扩展到大于第一深度的第二深度，并且第二蚀刻形成第二蚀刻特征。 然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。
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公开(公告)号：US08957519B2
公开(公告)日：2015-02-17
申请号：US12910075
申请日：2010-10-22
申请人： Chih-Chao Yang , Hsueh-Chung Chen
发明人： Chih-Chao Yang , Hsueh-Chung Chen
IPC分类号： H01L23/48 , H01L21/321 , H01L21/02 , H01L21/768
CPC分类号： H01L21/321 , H01L21/02304 , H01L21/76852 , H01L21/76886
摘要： The problem of poor adherence of a dielectric coating on a patterned metal structure can be solved by forming an adhesion layer on exposed surfaces of such metal structure prior to deposition of such dielectric. According to an embodiment, the invention provides a method to form a self-aligned adhesion layer on the surface of metal interconnect structure within an integrated circuit by exposing the metal structure to a controlled atmosphere and a flow of nitrogen-containing gas.
摘要翻译： 可以通过在沉积这种电介质之前在这种金属结构的暴露表面上形成粘合层来解决图案化金属结构上的电介质涂层粘附性差的问题。 根据一个实施例，本发明提供了一种通过将金属结构暴露于受控气氛和含氮气体的流动来在集成电路内的金属互连结构的表面上形成自对准粘附层的方法。
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10.发明授权Discontinuous/non-uniform metal cap structure and process for interconnect integration 有权不连续/不均匀的金属帽结构和互连整合的过程公开(公告)号：US08889546B2
公开(公告)日：2014-11-18
申请号：US13600773
申请日：2012-08-31
申请人： Chih-Chao Yang , Lynne M. Gignac , Chao-Kun Hu , Surbhi Mittal
发明人： Chih-Chao Yang , Lynne M. Gignac , Chao-Kun Hu , Surbhi Mittal
IPC分类号： H01L21/4763 , H01L23/532 , H01L23/528 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/02362 , H01L21/76849 , H01L21/76865 , H01L21/76868 , H01L23/5283 , H01L23/53223 , H01L23/53252 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating an interconnect structure is provided which includes providing a dielectric material having a dielectric constant of about 3.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material; and forming a noble metal-containing cap directly on the upper surface of the at least one conductive material, wherein the noble metal cap is discontinuous or non-uniform.
摘要翻译： 提供一种制造互连结构的方法，其包括提供具有约3.0或更小介电常数的介电材料和嵌入其中的至少一种导电材料，所述至少一种导电材料具有与上表面共面的上表面 的介电材料; 并且在所述至少一种导电材料的上表面上直接形成含贵金属的帽，其中所述贵金属帽是不连续的或不均匀的。
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