公开(公告)号：US20130182490A1

公开(公告)日：2013-07-18

申请号：US13477901

申请日：2012-05-22

申请人： Xiaowei Deng ,  Wah Kit Loh ,  Anand Seshadri ,  Zhonghai Shi

发明人： Xiaowei Deng ,  Wah Kit Loh ,  Anand Seshadri ,  Zhonghai Shi

IPC分类号： G11C11/40 ,  H01L21/82

CPC分类号： G11C11/413 ,  G11C11/412 ,  H01L27/1104

摘要： Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature.

摘要翻译： 在具有不对称上下文（例如缓冲电路）的静态随机存取存储器（SRAM）单元中的平衡电性能。 每个存储单元包括诸如读缓冲器的电路特征，其具有比单元内的其它晶体管更大的晶体管尺寸和特征，并且其中特征不对称影响较小单元晶体管。 为了获得最佳性能，单元晶体管对将彼此电气匹配。 更接近不对称特征的单元晶体管中的一个或多个不同地构成，例如具有不同的沟道宽度，沟道长度或净沟道掺杂剂浓度，以补偿不对称特征的邻近效应。

公开(公告)号：US08472228B2

公开(公告)日：2013-06-25

申请号：US12913479

申请日：2010-10-27

申请人： Xiaowei Deng ,  Wah Kit Loh ,  Anand Seshadri ,  Terence G. W. Blake

发明人： Xiaowei Deng ,  Wah Kit Loh ,  Anand Seshadri ,  Terence G. W. Blake

IPC分类号： G11C5/02 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  G11C5/025 ,  Y02P90/265

摘要： An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array.

公开(公告)号：US20120324314A1

公开(公告)日：2012-12-20

申请号：US13483897

申请日：2012-05-30

申请人： Anand Seshadri ,  Wah Kit Loh

发明人： Anand Seshadri ,  Wah Kit Loh

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1048 ,  G11C11/41 ,  G11C29/42 ,  G11C29/50016 ,  H03M13/13 ,  H03M13/19

摘要： Solid-state random access memory including error correction capability applied to memory arrays entering and exiting a data retention mode. Error correction coding of the data to be retained is performed upon determining that a portion of the memory is to enter data retention mode; the parity bits (i.e., bits in addition to those required for storage of the payload) are stored in available memory cells within or external to the retention domain. Upon exit from retention mode, the code words are decoded to correct any errors, and the payload data are returned to the original cells. Error correction encoding and decoding is not performed in the normal operating mode.

摘要翻译： 固态随机存取存储器包括应用于进入和退出数据保留模式的存储器阵列的纠错能力。 在确定存储器的一部分要进入数据保持模式时执行要保留的数据的纠错编码; 奇偶校验位（即除了存储有效载荷所需的位之外的位）存储在保留域内或外部的可用存储单元中。 退出保留模式后，对代码字进行解码以纠正任何错误，并将有效载荷数据返回到原始单元格。 在正常工作模式下不进行纠错编码和解码。

公开(公告)号：US20120106225A1

公开(公告)日：2012-05-03

申请号：US12913479

申请日：2010-10-27

申请人： Xiaowei Deng ,  Wah Kit Loh ,  Anand Seshadri ,  Terence G. W. Blake

发明人： Xiaowei Deng ,  Wah Kit Loh ,  Anand Seshadri ,  Terence G. W. Blake

IPC分类号： G11C5/02 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  G11C5/025 ,  Y02P90/265

摘要： An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array.

摘要翻译： 一种用于生成集成电路的布局的集成电路和方法，其中根据类似于单元本身构造的器件在一个或多个结构级别中实现诸如存储器或逻辑单元的重复特征阵列的外围电路。 确定在各种水平上引起邻近效应的距离。 这些接近效应距离决定了在每个级别的阵列之外和之后重复的那些特征的数量，其中构造外围电路以匹配阵列中的重复特征的构造。

公开(公告)号：US08654562B2

公开(公告)日：2014-02-18

申请号：US13477901

申请日：2012-05-22

申请人： Xiaowei Deng ,  Wah Kit Loh ,  Anand Seshadri ,  Zhonghai Shi

发明人： Xiaowei Deng ,  Wah Kit Loh ,  Anand Seshadri ,  Zhonghai Shi

IPC分类号： G11C11/00

CPC分类号： G11C11/413 ,  G11C11/412 ,  H01L27/1104

摘要： Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature.

摘要翻译： 在具有不对称上下文（例如缓冲电路）的静态随机存取存储器（SRAM）单元中的平衡电性能。 每个存储单元包括诸如读缓冲器的电路特征，其具有比单元内的其它晶体管更大的晶体管尺寸和特征，并且其中特征不对称影响较小单元晶体管。 为了获得最佳性能，单元晶体管对将彼此电气匹配。 更接近不对称特征的单元晶体管中的一个或多个不同地构成，例如具有不同的沟道宽度，沟道长度或净沟道掺杂剂浓度，以补偿不对称特征的邻近效应。

公开(公告)号：US08560931B2

公开(公告)日：2013-10-15

申请号：US13483897

申请日：2012-05-30

申请人： Anand Seshadri ,  Wah Kit Loh

发明人： Anand Seshadri ,  Wah Kit Loh

IPC分类号： G06F11/00 ,  H03M13/00 ,  G11C5/14

CPC分类号： G06F11/1048 ,  G11C11/41 ,  G11C29/42 ,  G11C29/50016 ,  H03M13/13 ,  H03M13/19

摘要： Solid-state random access memory including error correction capability applied to memory arrays entering and exiting a data retention mode. Error correction coding of the data to be retained is performed upon determining that a portion of the memory is to enter data retention mode; the parity bits (i.e., bits in addition to those required for storage of the payload) are stored in available memory cells within or external to the retention domain. Upon exit from retention mode, the code words are decoded to correct any errors, and the payload data are returned to the original cells. Error correction encoding and decoding is not performed in the normal operating mode.

摘要翻译： 固态随机存取存储器包括应用于进入和退出数据保留模式的存储器阵列的纠错能力。 在确定存储器的一部分要进入数据保持模式时执行要保留的数据的纠错编码; 奇偶校验位（即除了存储有效载荷所需的位之外的位）存储在保留域内或外部的可用存储单元中。 退出保留模式后，对代码字进行解码以纠正任何错误，并将有效载荷数据返回到原始单元格。 在正常工作模式下不进行纠错编码和解码。

公开(公告)号：US08971138B2

公开(公告)日：2015-03-03

申请号：US13467517

申请日：2012-05-09

申请人： Anand Seshadri ,  Wah Kit Loh

发明人： Anand Seshadri ,  Wah Kit Loh

IPC分类号： G11C29/00 ,  G11C29/50 ,  G11C29/04 ,  G11C29/06 ,  G11C11/41

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/06 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/5002

摘要： A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for n-channel transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, static noise margin and writeability (Vtrip) screens are provided. Each of the n-channel transistors in the CMOS SRAM cells are formed within p-wells that are isolated from p-type semiconductor material in peripheral circuitry of the memory and other functions in the integrated circuit. Forward and reverse body node bias voltages are applied to the isolated p-wells of the SRAM cells under test to determine whether such operations as read disturb, or write cycles, disrupt the cells under such bias. Cells that are vulnerable to threshold voltage shift over time can thus be identified.

摘要翻译： 一种互补金属氧化物半导体CMOS集成电路的方法，例如包括CMOS静态随机存取存储器（SRAM）单元的集成电路，用于易于经过工作时间的晶体管特性偏移的n沟道晶体管。 对于由交叉耦合CMOS反相器形成的SRAM单元的示例，提供静态噪声容限和可写性（Vtrip）屏幕。 CMOS SRAM单元中的每个n沟道晶体管形成在与存储器的外围电路中的p型半导体材料和集成电路中的其它功能隔离的p阱内。 正向和反向体节点偏置电压被施加到待测SRAM单元的隔离p阱，以确定读取干扰或写周期这样的操作是否会在这种偏差下破坏单元。 因此可以识别易受阈值电压偏移的电池。

公开(公告)号：US20130058177A1

公开(公告)日：2013-03-07

申请号：US13467517

申请日：2012-05-09

申请人： Anand Seshadri ,  Wah Kit Loh

发明人： Anand Seshadri ,  Wah Kit Loh

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/06 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/5002

摘要： A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for n-channel transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, static noise margin and writeability (Vtrip) screens are provided. Each of the n-channel transistors in the CMOS SRAM cells are formed within p-wells that are isolated from p-type semiconductor material in peripheral circuitry of the memory and other functions in the integrated circuit. Forward and reverse body node bias voltages are applied to the isolated p-wells of the SRAM cells under test to determine whether such operations as read disturb, or write cycles, disrupt the cells under such bias. Cells that are vulnerable to threshold voltage shift over time can thus be identified.

摘要翻译： 一种互补金属氧化物半导体CMOS集成电路的方法，例如包括CMOS静态随机存取存储器（SRAM）单元的集成电路，用于易于经过工作时间的晶体管特性偏移的n沟道晶体管。 对于由交叉耦合CMOS反相器形成的SRAM单元的示例，提供静态噪声容限和可写性（Vtrip）屏幕。 CMOS SRAM单元中的每个n沟道晶体管形成在与存储器的外围电路中的p型半导体材料和集成电路中的其它功能隔离的p阱内。 正向和反向体节点偏置电压被施加到待测SRAM单元的隔离p阱，以确定读取干扰或写周期这样的操作是否会在这种偏差下破坏单元。 因此可以识别易受阈值电压偏移的电池。

公开(公告)号：US08542545B2

公开(公告)日：2013-09-24

申请号：US13070799

申请日：2011-03-24

申请人： Wah Kit Loh ,  Beena Pious

发明人： Wah Kit Loh ,  Beena Pious

IPC分类号： G11C29/00

CPC分类号： G11C11/417 ,  G11C11/412 ,  G11C29/52

摘要： An embodiment of the invention provides a method of repairing soft failures in memory cells of an SRAM array. The SRAM array is tested to determine the location and type of soft failures in the memory cells. An assist circuit is activated that changes a voltage in a group of memory cells with the same type of soft failure. The change in voltage created by the assist circuit repairs the soft failures in the group. The group may be a word line or a bit line. The type of soft failures includes a failure during a read of a memory cell and a failure during the write of a memory cell.

摘要翻译： 本发明的实施例提供了修复SRAM阵列的存储单元中的软故障的方法。 测试SRAM阵列以确定存储器单元中软故障的位置和类型。 激活辅助电路，其改变具有相同类型的软故障的一组存储器单元中的电压。 辅助电路产生的电压变化会修复组中的软故障。 该组可以是字线或位线。 软故障的类型包括在存储器单元的读取期间的故障和在存储器单元写入期间的故障。

公开(公告)号：US07924640B2

公开(公告)日：2011-04-12

申请号：US11945469

申请日：2007-11-27

申请人： Xiaowei Deng ,  Wah Kit Loh

发明人： Xiaowei Deng ,  Wah Kit Loh

IPC分类号： G11C29/00

CPC分类号： G11C29/006 ,  G11C11/413 ,  G11C2029/0403 ,  H01L22/34 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807

摘要： A test method includes providing an integrated circuit, where the integrated circuit includes a memory base cell, where the memory base cell includes a first storage node set, a second storage node set, a set of other nodes, and a set of circuit elements each having a plurality of terminals, where the set of other nodes includes a first data node for accessing the first storage node set, a first access control node for controlling the access of the first storage node set, a first supply node for supplying the first storage node set, and a second supply node for supplying the second storage node set, where the first and second supply nodes are of the same sinking or sourcing type. The method further includes conducting a circuit element test on a circuit element in the set of circuit elements, where in the circuit element test the first and second supply nodes are not connected together, each terminal of the circuit element is directly forced with an electrical quantity, and an electrical quantity is directly measured from a terminal of the circuit element. Further, the method includes conducting at least one of a static noise margin test or a full cell test on the memory base cell.

摘要翻译： 测试方法包括提供集成电路，其中集成电路包括存储器基本单元，其中存储器基本单元包括第一存储节点集合，第二存储节点集合，一组其他节点以及各组电路元件 具有多个终端，其中所述一组其他节点包括用于访问所述第一存储节点集的第一数据节点，用于控制所述第一存储节点集合的访问的第一访问控制节点，用于提供所述第一存储 节点集合，以及用于提供第二存储节点集合的第二供应节点，其中第一和第二供应节点具有相同的下沉或采购类型。 该方法还包括对电路元件集合中的电路元件进行电路元件测试，其中在电路元件测试中，第一和第二供电节点未连接在一起，电路元件的每个端子被直接用电量强制 ，并且从电路元件的端子直接测量电量。 此外，该方法包括在存储器基本单元上执行静态噪声容限测试或全单元测试中的至少一个。