公开(公告)号：US07392352B2

公开(公告)日：2008-06-24

申请号：US11176518

申请日：2005-07-07

申请人： Arvind Mithal ,  Xiaowei Shen ,  Lawrence Rogel

发明人： Arvind Mithal ,  Xiaowei Shen ,  Lawrence Rogel

IPC分类号： G06F12/00

CPC分类号： G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F12/0817 ,  G06F12/0826 ,  G06F12/084

摘要： A computer architecture that includes a hierarchical memory system and one or more processors. The processors execute memory access instructions whose semantics are defined in terms of the hierarchical structure of the memory system. That is, rather than attempting to maintain the illusion that the memory system is shared by all processors such that changes made by one processor are immediately visible to other processors, the memory access instructions explicitly address access to a processor-specific memory, and data transfer between the processor-specific memory and the shared memory system. Various alternative embodiments of the memory system are compatible with these instructions. These alternative embodiments do not change the semantic meaning of a computer program which uses the memory access instructions, but allow different approaches to how and when data is actually passed from one processor to another.

摘要翻译： 包括分层存储器系统和一个或多个处理器的计算机体系结构。 处理器执行存储器访问指令，其语义是根据存储器系统的层次结构定义的。 也就是说，不是试图保持所有处理器共享存储器系统的错觉，使得一个处理器所做的改变对于其他处理器是立即可见的，所以存储器访问指令明确地解决对处理器特定存储器的访问以及数据传输 在处理器特定的存储器和共享存储器系统之间。 存储器系统的各种替代实施例与这些指令兼容。 这些替代实施例不改变使用存储器访问指令的计算机程序的语义含义，而是允许不同的方法来实现数据从一个处理器到另一处理器的实际传递。

公开(公告)号：US20060004967A1

公开(公告)日：2006-01-05

申请号：US11176518

申请日：2005-07-07

申请人： Arvind Mithal ,  Xiaowei Shen ,  Lawrence Rogel

发明人： Arvind Mithal ,  Xiaowei Shen ,  Lawrence Rogel

IPC分类号： G06F12/00

CPC分类号： G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F12/0817 ,  G06F12/0826 ,  G06F12/084

摘要： A computer architecture that includes a hierarchical memory system and one or more processors. The processors execute memory access instructions whose semantics are defined in terms of the hierarchical structure of the memory system. That is, rather than attempting to maintain the illusion that the memory system is shared by all processors such that changes made by one processor are immediately visible to other processors, the memory access instructions explicitly address access to a processor-specific memory, and data transfer between the processor-specific memory and the shared memory system. Various alternative embodiments of the memory system are compatible with these instructions. These alternative embodiments do not change the semantic meaning of a computer program which uses the memory access instructions, but allow different approaches to how and when data is actually passed from one processor to another.

公开(公告)号：US06757787B2

公开(公告)日：2004-06-29

申请号：US10325028

申请日：2002-12-19

申请人： Xiaowei Shen ,  Arvind Mithal ,  Lawrence Rogel

发明人： Xiaowei Shen ,  Arvind Mithal ,  Lawrence Rogel

IPC分类号： G06F1200

CPC分类号： G06F12/0826 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0817

摘要： A methodology for designing a distributed shared-memory system, which can incorporate adaptation or selection of cache protocols during operation, guarantees semantically correct processing of memory instructions by the multiple processors. A set of rules includes a first subset of “mandatory” rules and a second subset of “voluntary” rules such that correct operation of the memory system is provided by application of all of the mandatory rules and selective application of the voluntary rules. A policy for enabling voluntary rules specifies a particular coherent cache protocol. The policy can include various types of adaptation and selection of different operating modes for different addresses and at different caches. A particular coherent cache protocol can make use of a limited capacity directory in which some but not necessarily all caches that hold a particular address are identified in the directory. In another coherent cache protocol, various caches hold an address in different modes which, for example, affect communication between a cache and a shared memory in processing particular memory instructions.

摘要翻译： 用于设计分布式共享存储器系统的方法，其可以在操作期间结合适应或选择高速缓存协议，保证了多处理器对存储器指令的语义上正确的处理。 一组规则包括“强制性”规则的第一子集和“自愿”规则的第二子集，从而通过应用所有强制性规则并选择性地应用自愿规则来提供存储系统的正确操作。 启用自愿规则的策略规定了特定的一致高速缓存协议。 该策略可以包括各种类型的适配和针对不同地址和不同高速缓存的不同操作模式的选择。 特定的一致高速缓存协议可以使用有限容量的目录，其中在目录中识别出一些但不一定所有保存特定地址的高速缓存。 在另一个相干高速缓存协议中，各种高速缓存以不同的模式保存地址，这些地址例如在处理特定的存储器指令时影响高速缓存和共享存储器之间的通信。

公开(公告)号：US06636950B1

公开(公告)日：2003-10-21

申请号：US09300641

申请日：1999-04-27

申请人： Arvind Mithal ,  Xiaowei Shen ,  Lawrence Rogel

发明人： Arvind Mithal ,  Xiaowei Shen ,  Lawrence Rogel

IPC分类号： G06F1200

CPC分类号： G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F12/0817 ,  G06F12/0826 ,  G06F12/084

摘要： A computer architecture that includes a hierarchical memory system and one or more processors. The processors execute memory access instructions whose semantics are defined in terms of the hierarchical structure of the memory system. That is, rather than attempting to maintain the illusion that the memory system is shared by all processors such that changes made by one processor are immediately visible to other processors, the memory access instructions explicitly address access to a processor-specific memory, and data transfer between the processor-specific memory and the shared memory system. Various alternative embodiments of the memory system are compatible with these instructions. These alternative embodiments do not change the semantic meaning of a computer program which uses the memory access instructions, but allow different approaches to how and when data is actually passed from one processor to another.

摘要翻译： 包括分层存储器系统和一个或多个处理器的计算机体系结构。 处理器执行存储器访问指令，其语义是根据存储器系统的层次结构定义的。 也就是说，不是试图保持所有处理器共享存储器系统的错觉，使得一个处理器所做的改变对于其他处理器是立即可见的，所以存储器访问指令明确地解决对处理器特定存储器的访问以及数据传输 在处理器特定的存储器和共享存储器系统之间。 存储器系统的各种替代实施例与这些指令兼容。 这些替代实施例不改变使用存储器访问指令的计算机程序的语义含义，而是允许不同的方法来实现数据从一个处理器到另一处理器的实际传递。

公开(公告)号：US06526481B1

公开(公告)日：2003-02-25

申请号：US09561168

申请日：2000-04-27

申请人： Xiaowei Shen ,  Arvind Mithal ,  Lawrence Rogel

发明人： Xiaowei Shen ,  Arvind Mithal ,  Lawrence Rogel

IPC分类号： C06F1200

CPC分类号： G06F12/0826 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0817

摘要： A methodology for designing a distributed shared-memory system, which can incorporate adaptation or selection of cache protocols during operation, guarantees semantically correct processing of memory instructions by the multiple processors. A set of rules includes a first subset of “mandatory” rules and a second subset of “voluntary” rules such that correct operation of the memory system is provided by application of all of the mandatory rules and selective application of the voluntary rules. A policy for enabling voluntary rules specifies a particular coherent cache protocol. The policy can include various types of adaptation and selection of different operating modes for different addresses and at different caches. A particular coherent cache protocol can make use of a limited capacity directory in which some but not necessarily all caches that hold a particular address are identified in the directory. In another coherent cache protocol, various caches hold an address in different modes which, for example, affect communication between a cache and a shared memory in processing particular memory instructions.

摘要翻译： 用于设计分布式共享存储器系统的方法，其可以在操作期间结合适应或选择高速缓存协议，保证了多处理器对存储器指令的语义上正确的处理。 一组规则包括“强制性”规则的第一子集和“自愿”规则的第二子集，从而通过应用所有强制性规则并选择性地应用自愿规则来提供存储系统的正确操作。 启用自愿规则的策略规定了特定的一致高速缓存协议。 该策略可以包括各种类型的适配和针对不同地址和不同高速缓存的不同操作模式的选择。 特定的一致高速缓存协议可以使用有限容量的目录，其中在目录中识别出一些但不一定所有保存特定地址的高速缓存。 在另一个相干高速缓存协议中，各种高速缓存以不同的模式保存地址，这些地址例如在处理特定的存储器指令时影响高速缓存和共享存储器之间的通信。

公开(公告)号：US08131938B2

公开(公告)日：2012-03-06

申请号：US12248209

申请日：2008-10-09

申请人： Xiaowei Shen ,  Man Cheuk Ng ,  Aaron Christoph Sawdey

发明人： Xiaowei Shen ,  Man Cheuk Ng ,  Aaron Christoph Sawdey

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0804 ,  G06F12/0831 ,  G06F2212/1016 ,  G06F2212/507

摘要： In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, it needs to be written back to the high-level cache; otherwise it can be simply flushed from the low-level cache. The high-level cache can employ a volatile-prediction mechanism that adaptively determines whether a volatile copy or a non-volatile copy should be supplied when the high-level cache needs to send data to the low-level cache. An exemplary volatile-prediction mechanism suggests use of a non-volatile copy if the cache line has been accessed consecutively by the low-level cache. Further, the low-level cache can employ a volatile-promotion mechanism that adaptively changes a data copy from volatile to non-volatile according to some promotion policy, or changes a data copy from non-volatile to volatile according to some demotion policy.

摘要翻译： 在具有存储器层次结构的计算机系统中，当高级缓存将数据拷贝提供给低级缓存时，共享副本可以是易失性的或非易失性的。 当数据拷贝稍后从低级缓存中替换时，如果数据拷贝是非易失性的，则需要将其写回高级缓存; 否则可以从低级缓存中简单地刷新。 高级缓存可以采用易失性预测机制，其自动地确定当高级缓存需要向低级缓存发送数据时是否应提供易失性拷贝或非易失性拷贝。 示例性的易失性预测机制建议如果高速缓存行已被低级缓存连续访问，则使用非易失性拷贝。 此外，低级缓存可以使用根据某些促销策略自动地将数据拷贝从易失性地改变为非易失性的易失性促进机制，或者根据某种降级策略将数据拷贝从非易失性变为不稳定。

公开(公告)号：US20110107032A1

公开(公告)日：2011-05-05

申请号：US12985726

申请日：2011-01-06

申请人： Xiaowei Shen ,  Balaram Sinharoy ,  Robert B. Tremaine ,  Robert W. Wisniewski

发明人： Xiaowei Shen ,  Balaram Sinharoy ,  Robert B. Tremaine ,  Robert W. Wisniewski

IPC分类号： G06F12/08

CPC分类号： G06F12/0864 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13

摘要： A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.

摘要翻译： 提供了一种重新配置高速缓冲存储器的方法。 一个方面中的方法可以包括分析访问高速缓冲存储器的执行实体的一个或多个特征，并且基于所分析的一个或多个特征重新配置高速缓存。 分析特性的示例可以包括但不限于执行实体使用的数据结构，执行实体的预期参考模式，执行实体的类型，执行实体的热和功耗。等等 重新配置可以包括但不限于高速缓冲存储器的相关性，可用于存储数据的高速缓冲存储器的量，高速缓冲存储器的相干粒度，高速缓存存储器的行大小等。

公开(公告)号：US20100138571A1

公开(公告)日：2010-06-03

申请号：US12623496

申请日：2009-11-23

申请人： Harold Wade Cain, III ,  Rui Hou ,  Xiaowei Shen ,  Huayong Wang

发明人： Harold Wade Cain, III ,  Rui Hou ,  Xiaowei Shen ,  Huayong Wang

IPC分类号： G06F5/14 ,  G06F9/46

CPC分类号： G06F9/30087 ,  G06F9/467 ,  G06F9/5016

摘要： A system, method, and computer readable article of manufacture for sharing buffer management. The system includes: a predictor module to predict at runtime a transaction data size of a transaction according to history information of the transaction; and a resource management module to allocate sharing buffer resources for the transaction according to the predicted transaction data size in response to beginning of the transaction, to record an actual sharing buffer size occupied by the transaction in response to the successful commitment of the transaction, and to update the history information of the transaction.

摘要翻译： 用于共享缓冲区管理的系统，方法和计算机可读制造品。 该系统包括：预测器模块，用于根据交易的历史信息在运行时预测交易的交易数据大小; 以及资源管理模块，用于响应于所述事务的开始，根据预测的事务数据大小来分配所述事务的共享缓冲器资源，以响应所述事务的成功承诺来记录所述事务所占用的实际共享缓冲区大小;以及 更新交易的历史信息。

公开(公告)号：US07574562B2

公开(公告)日：2009-08-11

申请号：US11491413

申请日：2006-07-21

申请人： Xiaowei Shen ,  Balaram Sinharoy ,  Robert W. Wisniewski

发明人： Xiaowei Shen ,  Balaram Sinharoy ,  Robert W. Wisniewski

IPC分类号： G06F12/02

CPC分类号： G06F12/0842 ,  G06F2212/271

摘要： A system and method for latency-aware thread scheduling in non-uniform cache architecture are provided. Instructions may be provided to the hardware specifying in which banks to store data. Information as to which banks store which data may also be provided, for example, by the hardware. This information may be used to schedule threads on one or more cores. A selected bank in cache memory may be reserved strictly for selected data.

摘要翻译： 提供了一种用于在非均匀缓存体系结构中进行延迟识别的线程调度的系统和方法。 可以向硬件提供指令，指定哪些存储体存储数据。 关于哪些银行存储哪些数据的信息也可以由硬件提供。 该信息可用于在一个或多个核心上调度线程。 高速缓冲存储器中的选定存储区可能被严格保留用于所选数据。

公开(公告)号：US20090043966A1

公开(公告)日：2009-02-12

申请号：US12248209

申请日：2008-10-09

申请人： Xiaowei Shen ,  Man Cheuk Ng ,  Aaron Christoph Sawdey

发明人： Xiaowei Shen ,  Man Cheuk Ng ,  Aaron Christoph Sawdey

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0804 ,  G06F12/0831 ,  G06F2212/1016 ,  G06F2212/507

摘要： In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, it needs to be written back to the high-level cache; otherwise it can be simply flushed from the low-level cache. The high-level cache can employ a volatile-prediction mechanism that adaptively determines whether a volatile copy or a non-volatile copy should be supplied when the high-level cache needs to send data to the low-level cache. An exemplary volatile-prediction mechanism suggests use of a non-volatile copy if the cache line has been accessed consecutively by the low-level cache. Further, the low-level cache can employ a volatile-promotion mechanism that adaptively changes a data copy from volatile to non-volatile according to some promotion policy, or changes a data copy from non-volatile to volatile according to some demotion policy.

摘要翻译： 在具有存储器层次结构的计算机系统中，当高级缓存将数据拷贝提供给低级缓存时，共享副本可以是易失性的或非易失性的。 当数据拷贝稍后从低级缓存中替换时，如果数据拷贝是非易失性的，则需要将其写回高级缓存; 否则可以从低级缓存中简单地刷新。 高级缓存可以采用易失性预测机制，其自动地确定当高级缓存需要向低级缓存发送数据时是否应提供易失性拷贝或非易失性拷贝。 示例性的易失性预测机制建议如果高速缓存行已被低级缓存连续访问，则使用非易失性拷贝。 此外，低级缓存可以使用根据某些促销策略自动地将数据拷贝从易失性地改变为非易失性的易失性促进机制，或者根据某种降级策略将数据拷贝从非易失性变为不稳定。