摘要:
A fluorine-free integrated process for plasma etching aluminum lines in an integrated circuit structure including an overlying anti-reflection coating (ARC) and a dielectric layer underlying the aluminum, the process being preferably performed in a single plasma reactor. The ARC open uses either BCl3/Cl2 or Cl2 and possibly a hydrocarbon passivating gas, preferably C2H4. The aluminum main etch preferably includes BCl3/Cl2 etch and C2H4 diluted with He. The dilution is particularly effective for small flow rates of C2H4. An over etch into the Ti/TiN barrier layer and part way into the underlying dielectric may use a chemistry similar to the main etch. A Cl2/O2 chamber cleaning may be performed, preferably with the wafer removed from the chamber and after every wafer cycle.
摘要翻译:一种用于等离子体蚀刻铝线的无氟集成方法,其集成电路结构包括上覆抗反射涂层(ARC)和铝下方的介电层,该方法优选在单个等离子体反应器中进行。 ARC打开使用BCl 3 / Cl 2 2或Cl 2 2和可能的烃钝化气体,优选C 2 H 2 > H 4。 铝主蚀刻优选包括用He稀释的BCl 3 / Cl 2 N 2蚀刻和C 2 H 2 H 4。 稀释度对于C 2 H 4 H 4的小流量特别有效。 对Ti / TiN阻挡层进行过度蚀刻并且部分地进入下面的电介质可以使用类似于主蚀刻的化学。 优选地,可以从晶片上取出晶片并在每个晶片周期之后进行C1 / 2 / O 2/2室清洁。
摘要:
One embodiment of the present invention is a process for etching an organic anti-reflective coating on a base of a substrate, the process including steps of: (a) placing the substrate into a processing chamber; (b) introducing into the processing chamber a processing gas including one or more of carbon monoxide (CO), carbon dioxide (CO2), and sulfur oxide (SO2); and (c) forming a plasma from the processing gas to etch the organic anti-reflective coating layer.
摘要:
Disclosed herein is a cleaning method useful in removing contaminants from a surface of a coating which comprises an oxide or fluoride of a Group III B metal. Typically the coating overlies an aluminum substrate which is present as part of a semiconductor processing apparatus. The coating typically comprises an oxide or a fluoride of Y, Sc, La, Ce, Eu, Dy, or the like, or yttrium-aluminum-garnet (YAG). The coating may further comprise about 20 volume % or less of Al2O3.
摘要:
A process for etching a substrate 25 in an etching chamber 30, and simultaneously cleaning a thin, non-homogeneous, etch residue deposited on the surfaces of the walls 45 and components of the etching chamber 30. In the etching step, process gas comprising etchant gas is used to etch a substrate 25 in the etching chamber 30 thereby depositing etch residue inside the chamber 30. Cleaning gas is added to the process gas for a sufficient time and in a volumetric flow ratio that is sufficiently high, to react with and remove substantially all the etch residue deposited by the process gas. The present method advantageously cleans the etch residue in the chamber 30, during the etching process, and without use of separate cleaning, conditioning, and seasoning process steps.
摘要:
Disclosed herein is a gas distribution plate for use in a gas distribution assembly for a processing chamber, where the gas distribution plate is fabricated from a solid yttrium oxide-comprising substrate, which may also include aluminum oxide. The gas distribution plate includes a plurality of through-holes, which are typically crescent-shaped. Through-holes which have been formed in the solid yttrium oxide-comprising substrate by ultrasonic drilling perform particularly well. The solid yttrium oxide-comprising substrate typically comprises at least 99.9% yttrium oxide, and has a density of at least 4.92 g/cm3, a water absorbency of about 0.02% or less, and an average grain size within the range of about 10 μm to about 25 μm. Also disclosed herein are methods for fabricating and cleaning the yttrium oxide-comprising gas distribution plate.
摘要翻译:本文公开了一种用于处理室的气体分配组件中的气体分配板,其中气体分配板由可能还包括氧化铝的固体含氧化钇衬底制成。 气体分配板包括通常为月牙形的多个通孔。 通过超声波钻孔在固体含氧化钇基质中形成的通孔特别好。 固体含氧化钇的基材通常包含至少99.9%的氧化钇,并且具有至少4.92g / cm 3的密度,约0.02%或更低的吸水率,以及在约10μm的范围内的平均晶粒尺寸 至约25μm。 本文还公开了用于制造和清洁含氧化钇气体分配板的方法。
摘要:
Methods for forming anisotropic features for high aspect ratio application in etch process are provided in the present invention. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios through a sidewall passivation management scheme. In one embodiment, sidewall passivations are managed by selectively forming an oxidation passivation layer on the sidewall and/or bottom of etched layers. In another embodiment, sidewall passivation is managed by periodically clearing the overburden redeposition layer to preserve an even and uniform passivation layer thereon. The even and uniform passivation allows the features with high aspect ratios to be incrementally etched in a manner that pertains a desired depth and vertical profile of critical dimension in both high and low feature density regions on the substrate without generating defects and/or overetching the underneath layers.
摘要:
In one implementation, a method is provided capable of etching a wafer to form devices including a high-k dielectric layer. The method includes etching an upper conductive material layer in a first plasma chamber with a low cathode temperature, transferring the wafer to a second chamber without breaking vacuum, etching a high-k dielectric layer in the second chamber, and transferring the wafer from the second chamber to the first plasma chamber without breaking vacuum. A lower conductive material layer is etched with a low cathode temperature in the first chamber. In one implementation, the high-k dielectric etch is a plasma etch using a high temperature cathode. In another implementation, the high-k dielectric etch is a reactive ion etch.
摘要:
Methods for forming anisotropic features for high aspect ratio application in etch process are provided in the present invention. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios through a sidewall passivation management scheme. In one embodiment, sidewall passivations are managed by selectively forming an oxidation passivation layer on the sidewall and/or bottom of etched layers. In another embodiment, sidewall passivation is managed by periodically clearing the overburden redeposition layer to preserve an even and uniform passivation layer thereon. The even and uniform passivation allows the features with high aspect ratios to be incrementally etched in a manner that pertains a desired depth and vertical profile of critical dimension in both high and low feature density regions on the substrate without generating defects and/or overetching the underneath layers.
摘要:
Disclosed herein is a gas distribution plate for use in a gas distribution assembly for a processing chamber, where the gas distribution plate is fabricated from a solid yttrium oxide-comprising substrate, which may also include aluminum oxide. The gas distribution plate includes a plurality of through-holes, which are typically crescent-shaped. Through-holes which have been formed in the solid yttrium oxide-comprising substrate by ultrasonic drilling perform particularly well. The solid yttrium oxide-comprising substrate typically comprises at least 99.9% yttrium oxide, and has a density of at least 4.92 g/cm3, a water absorbency of about 0.02% or less, and an average grain size within the range of about 10 μm to about 25 μm. Also disclosed herein are methods for fabricating and cleaning the yttrium oxide-comprising gas distribution plate.
摘要翻译:本文公开了一种用于处理室的气体分配组件中的气体分配板,其中气体分配板由可能还包括氧化铝的固体含氧化钇衬底制成。 气体分配板包括通常为月牙形的多个通孔。 通过超声波钻孔在固体含氧化钇基质中形成的通孔特别好。 固体含氧化钇的基材通常包含至少99.9%的氧化钇,并且具有至少4.92g / cm 3的密度,约0.02%或更低的吸水率,以及在约10μm的范围内的平均晶粒尺寸 至约25μm。 本文还公开了用于制造和清洁含氧化钇气体分配板的方法。
摘要:
In one implementation, a method is provided capable of etching a wafer to form devices including a high-k dielectric layer. The method includes etching an upper conductive material layer in a first plasma chamber with a low cathode temperature, transferring the wafer to a second chamber without breaking vacuum, etching a high-k dielectric layer in the second chamber, and transferring the wafer from the second chamber to the first plasma chamber without breaking vacuum. A lower conductive material layer is etched with a low cathode temperature in the first chamber. In one implementation, the high-k dielectric etch is a plasma etch using a high temperature cathode. In another implementation, the high-k dielectric etch is a reactive ion etch.