Fluorine free integrated process for etching aluminum including chamber dry clean
    1.
    发明授权
    Fluorine free integrated process for etching aluminum including chamber dry clean 失效
    无氟一体化蚀刻铝工艺,包括干燥室

    公开(公告)号:US07270761B2

    公开(公告)日:2007-09-18

    申请号:US10273580

    申请日:2002-10-18

    IPC分类号: H01L21/302

    摘要: A fluorine-free integrated process for plasma etching aluminum lines in an integrated circuit structure including an overlying anti-reflection coating (ARC) and a dielectric layer underlying the aluminum, the process being preferably performed in a single plasma reactor. The ARC open uses either BCl3/Cl2 or Cl2 and possibly a hydrocarbon passivating gas, preferably C2H4. The aluminum main etch preferably includes BCl3/Cl2 etch and C2H4 diluted with He. The dilution is particularly effective for small flow rates of C2H4. An over etch into the Ti/TiN barrier layer and part way into the underlying dielectric may use a chemistry similar to the main etch. A Cl2/O2 chamber cleaning may be performed, preferably with the wafer removed from the chamber and after every wafer cycle.

    摘要翻译: 一种用于等离子体蚀刻铝线的无氟集成方法,其集成电路结构包括上覆抗反射涂层(ARC)和铝下方的介电层,该方法优选在单个等离子体反应器中进行。 ARC打开使用BCl 3 / Cl 2 2或Cl 2 2和可能的烃钝化气体,优选C 2 H 2 > H 4。 铝主蚀刻优选包括用He稀释的BCl 3 / Cl 2 N 2蚀刻和C 2 H 2 H 4。 稀释度对于C 2 H 4 H 4的小流量特别有效。 对Ti / TiN阻挡层进行过度蚀刻并且部分地进入下面的电介质可以使用类似于主蚀刻的化学。 优选地,可以从晶片上取出晶片并在每个晶片周期之后进行C1 / 2 / O 2/2室清洁。

    Methods for etching an organic anti-reflective coating
    2.
    发明授权
    Methods for etching an organic anti-reflective coating 失效
    蚀刻有机抗反射涂层的方法

    公开(公告)号:US06649532B1

    公开(公告)日:2003-11-18

    申请号:US10143489

    申请日:2002-05-09

    IPC分类号: H01L21302

    摘要: One embodiment of the present invention is a process for etching an organic anti-reflective coating on a base of a substrate, the process including steps of: (a) placing the substrate into a processing chamber; (b) introducing into the processing chamber a processing gas including one or more of carbon monoxide (CO), carbon dioxide (CO2), and sulfur oxide (SO2); and (c) forming a plasma from the processing gas to etch the organic anti-reflective coating layer.

    摘要翻译: 本发明的一个实施方案是用于在衬底的基底上蚀刻有机抗反射涂层的方法,该方法包括以下步骤:(a)将衬底放置在处理室中; (b)将包括一氧化碳(CO),二氧化碳(CO 2)和硫氧化物(SO 2))中的一种或多种的处理气体引入处理室; 和(c)从处理气体形成等离子体以蚀刻有机抗反射涂层。

    Method of removing contaminants from a coating surface comprising an oxide or fluoride of a group IIIB metal
    3.
    发明申请
    Method of removing contaminants from a coating surface comprising an oxide or fluoride of a group IIIB metal 有权
    从包含IIIB族金属的氧化物或氟化物的涂层表面除去污染物的方法

    公开(公告)号:US20090025751A1

    公开(公告)日:2009-01-29

    申请号:US12284540

    申请日:2008-09-22

    IPC分类号: B08B3/08 B08B3/12

    摘要: Disclosed herein is a cleaning method useful in removing contaminants from a surface of a coating which comprises an oxide or fluoride of a Group III B metal. Typically the coating overlies an aluminum substrate which is present as part of a semiconductor processing apparatus. The coating typically comprises an oxide or a fluoride of Y, Sc, La, Ce, Eu, Dy, or the like, or yttrium-aluminum-garnet (YAG). The coating may further comprise about 20 volume % or less of Al2O3.

    摘要翻译: 本文公开了一种可用于从包含IIIBB族金属的氧化物或氟化物的涂层表面除去污染物的清洁方法。 通常,涂层覆盖作为半导体处理装置的一部分存在的铝基板。 涂层通常包含Y,Sc,La,Ce,Eu,Dy等的氧化物或氟化物,或钇 - 铝 - 石榴石(YAG)。 涂层可以进一步包含约20体积%或更少的Al 2 O 3。

    Self-cleaning etch process
    4.
    发明授权
    Self-cleaning etch process 失效
    自清洁蚀刻工艺

    公开(公告)号:US06699399B1

    公开(公告)日:2004-03-02

    申请号:US09657793

    申请日:2000-09-08

    IPC分类号: C23F400

    CPC分类号: H01L21/02071 Y10S438/905

    摘要: A process for etching a substrate 25 in an etching chamber 30, and simultaneously cleaning a thin, non-homogeneous, etch residue deposited on the surfaces of the walls 45 and components of the etching chamber 30. In the etching step, process gas comprising etchant gas is used to etch a substrate 25 in the etching chamber 30 thereby depositing etch residue inside the chamber 30. Cleaning gas is added to the process gas for a sufficient time and in a volumetric flow ratio that is sufficiently high, to react with and remove substantially all the etch residue deposited by the process gas. The present method advantageously cleans the etch residue in the chamber 30, during the etching process, and without use of separate cleaning, conditioning, and seasoning process steps.

    摘要翻译: 用于在蚀刻室30中蚀刻基板25并同时清洗沉积在壁45的表面上的薄的,非均匀的蚀刻残留物和蚀刻室30的部件的方法。在蚀刻步骤中,包括蚀刻剂的工艺气体 使用气体来蚀刻蚀刻室30中的衬底25,从而在腔室30内沉积蚀刻残留物。将清洁气体加入到工艺气体足够长的时间内,并以足够高的体积流量比与反应和去除 基本上所有由工艺气体沉积的蚀刻残留物。 本方法有利地在蚀刻过程期间清洁室30中的蚀刻残留物,并且不使用单独的清洁,调理和调味处理步骤。

    Cleaning method used in removing contaminants from a solid yttrium oxide-containing substrate
    5.
    发明授权
    Cleaning method used in removing contaminants from a solid yttrium oxide-containing substrate 有权
    用于从含固体含氧化钇的底物中除去污染物的清洁方法

    公开(公告)号:US07846264B2

    公开(公告)日:2010-12-07

    申请号:US11592905

    申请日:2006-11-03

    IPC分类号: B08B3/00

    摘要: Disclosed herein is a gas distribution plate for use in a gas distribution assembly for a processing chamber, where the gas distribution plate is fabricated from a solid yttrium oxide-comprising substrate, which may also include aluminum oxide. The gas distribution plate includes a plurality of through-holes, which are typically crescent-shaped. Through-holes which have been formed in the solid yttrium oxide-comprising substrate by ultrasonic drilling perform particularly well. The solid yttrium oxide-comprising substrate typically comprises at least 99.9% yttrium oxide, and has a density of at least 4.92 g/cm3, a water absorbency of about 0.02% or less, and an average grain size within the range of about 10 μm to about 25 μm. Also disclosed herein are methods for fabricating and cleaning the yttrium oxide-comprising gas distribution plate.

    摘要翻译: 本文公开了一种用于处理室的气体分配组件中的气体分配板,其中气体分配板由可能还包括氧化铝的固体含氧化钇衬底制成。 气体分配板包括通常为月牙形的多个通孔。 通过超声波钻孔在固体含氧化钇基质中形成的通孔特别好。 固体含氧化钇的基材通常包含至少99.9%的氧化钇,并且具有至少4.92g / cm 3的密度,约0.02%或更低的吸水率,以及在约10μm的范围内的平均晶粒尺寸 至约25μm。 本文还公开了用于制造和清洁含氧化钇气体分配板的方法。

    Etch methods to form anisotropic features for high aspect ratio applications
    6.
    发明授权
    Etch methods to form anisotropic features for high aspect ratio applications 失效
    蚀刻方法来形成高纵横比应用的各向异性特征

    公开(公告)号:US07368394B2

    公开(公告)日:2008-05-06

    申请号:US11363834

    申请日:2006-02-27

    IPC分类号: H01L21/461 H01L21/302

    摘要: Methods for forming anisotropic features for high aspect ratio application in etch process are provided in the present invention. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios through a sidewall passivation management scheme. In one embodiment, sidewall passivations are managed by selectively forming an oxidation passivation layer on the sidewall and/or bottom of etched layers. In another embodiment, sidewall passivation is managed by periodically clearing the overburden redeposition layer to preserve an even and uniform passivation layer thereon. The even and uniform passivation allows the features with high aspect ratios to be incrementally etched in a manner that pertains a desired depth and vertical profile of critical dimension in both high and low feature density regions on the substrate without generating defects and/or overetching the underneath layers.

    摘要翻译: 在本发明中提供了用于在蚀刻工艺中形成用于高纵横比应用的各向异性特征的方法。 本文描述的方法通过侧壁钝化管理方案有利地促进具有高纵横比的特征的轮廓和尺寸控制。 在一个实施例中,通过在蚀刻层的侧壁和/或底部选择性地形成氧化钝化层来管理侧壁钝化。 在另一个实施例中,通过周期性地清除覆盖层再沉积层以在其上保持均匀且均匀的钝化层来管理侧壁钝化。 均匀和均匀的钝化允许以在衬底上的高和低特征密度区域中具有临界尺寸的期望深度和垂直分布的方式来逐渐蚀刻具有高纵横比的特征,而不产生缺陷和/或过蚀刻下面 层。

    Device and method for etching flash memory gate stacks comprising high-k dielectric
    7.
    发明申请
    Device and method for etching flash memory gate stacks comprising high-k dielectric 有权
    用于蚀刻包括高k电介质的闪存存储器栅极堆叠的器件和方法

    公开(公告)号:US20070224813A1

    公开(公告)日:2007-09-27

    申请号:US11386054

    申请日:2006-03-21

    IPC分类号: C23F1/00 H01L21/302

    CPC分类号: H01L21/32136 H01L21/31116

    摘要: In one implementation, a method is provided capable of etching a wafer to form devices including a high-k dielectric layer. The method includes etching an upper conductive material layer in a first plasma chamber with a low cathode temperature, transferring the wafer to a second chamber without breaking vacuum, etching a high-k dielectric layer in the second chamber, and transferring the wafer from the second chamber to the first plasma chamber without breaking vacuum. A lower conductive material layer is etched with a low cathode temperature in the first chamber. In one implementation, the high-k dielectric etch is a plasma etch using a high temperature cathode. In another implementation, the high-k dielectric etch is a reactive ion etch.

    摘要翻译: 在一个实施方式中,提供了能够蚀刻晶片以形成包括高k电介质层的器件的方法。 该方法包括在具有低阴极温度的第一等离子体室中蚀刻上导电材料层,将晶片转移到第二室而不破坏真空,蚀刻第二室中的高k电介质层,以及从第二室转移晶片 室到第一等离子体室,而不破坏真空。 在第一室中以低阴极温度蚀刻下导电材料层。 在一个实施方案中,高k电介质蚀刻是使用高温阴极的等离子体蚀刻。 在另一个实施方案中,高k电介质蚀刻是反应离子蚀刻。

    ETCH METHODS TO FORM ANISOTROPIC FEATURES FOR HIGH ASPECT RATIO APPLICATIONS
    8.
    发明申请
    ETCH METHODS TO FORM ANISOTROPIC FEATURES FOR HIGH ASPECT RATIO APPLICATIONS 审中-公开
    ETCH方法形成高度比例应用的各向异性特征

    公开(公告)号:US20080057729A1

    公开(公告)日:2008-03-06

    申请号:US11926531

    申请日:2007-10-29

    IPC分类号: H01L21/465

    摘要: Methods for forming anisotropic features for high aspect ratio application in etch process are provided in the present invention. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios through a sidewall passivation management scheme. In one embodiment, sidewall passivations are managed by selectively forming an oxidation passivation layer on the sidewall and/or bottom of etched layers. In another embodiment, sidewall passivation is managed by periodically clearing the overburden redeposition layer to preserve an even and uniform passivation layer thereon. The even and uniform passivation allows the features with high aspect ratios to be incrementally etched in a manner that pertains a desired depth and vertical profile of critical dimension in both high and low feature density regions on the substrate without generating defects and/or overetching the underneath layers.

    摘要翻译: 在本发明中提供了用于在蚀刻工艺中形成用于高纵横比应用的各向异性特征的方法。 本文描述的方法通过侧壁钝化管理方案有利地促进具有高纵横比的特征的轮廓和尺寸控制。 在一个实施例中,通过在蚀刻层的侧壁和/或底部选择性地形成氧化钝化层来管理侧壁钝化。 在另一个实施例中,通过周期性地清除覆盖层再沉积层以在其上保持均匀且均匀的钝化层来管理侧壁钝化。 均匀和均匀的钝化允许以在衬底上的高和低特征密度区域中具有临界尺寸的期望深度和垂直分布的方式来逐渐蚀刻具有高纵横比的特征,而不产生缺陷和/或过蚀刻下面 层。

    Solid yttrium oxide-containing substrate which has been cleaned to remove impurities
    9.
    发明申请
    Solid yttrium oxide-containing substrate which has been cleaned to remove impurities 审中-公开
    固体含氧化钇基质已被清洗除去杂质

    公开(公告)号:US20110036874A1

    公开(公告)日:2011-02-17

    申请号:US12925271

    申请日:2010-10-18

    IPC分类号: B05B1/14

    摘要: Disclosed herein is a gas distribution plate for use in a gas distribution assembly for a processing chamber, where the gas distribution plate is fabricated from a solid yttrium oxide-comprising substrate, which may also include aluminum oxide. The gas distribution plate includes a plurality of through-holes, which are typically crescent-shaped. Through-holes which have been formed in the solid yttrium oxide-comprising substrate by ultrasonic drilling perform particularly well. The solid yttrium oxide-comprising substrate typically comprises at least 99.9% yttrium oxide, and has a density of at least 4.92 g/cm3, a water absorbency of about 0.02% or less, and an average grain size within the range of about 10 μm to about 25 μm. Also disclosed herein are methods for fabricating and cleaning the yttrium oxide-comprising gas distribution plate.

    摘要翻译: 本文公开了一种用于处理室的气体分配组件中的气体分配板,其中气体分配板由可能还包括氧化铝的固体含氧化钇衬底制成。 气体分配板包括通常为月牙形的多个通孔。 通过超声波钻孔在固体含氧化钇基质中形成的通孔特别好。 固体含氧化钇的基材通常包含至少99.9%的氧化钇,并且具有至少4.92g / cm 3的密度,约0.02%或更低的吸水率,以及在约10μm的范围内的平均晶粒尺寸 至约25μm。 本文还公开了用于制造和清洁含氧化钇气体分配板的方法。

    Device and method for etching flash memory gate stacks comprising high-k dielectric
    10.
    发明授权
    Device and method for etching flash memory gate stacks comprising high-k dielectric 有权
    用于蚀刻包括高k电介质的闪存存储器栅极堆叠的器件和方法

    公开(公告)号:US07780862B2

    公开(公告)日:2010-08-24

    申请号:US11386054

    申请日:2006-03-21

    IPC分类号: H01L21/302

    CPC分类号: H01L21/32136 H01L21/31116

    摘要: In one implementation, a method is provided capable of etching a wafer to form devices including a high-k dielectric layer. The method includes etching an upper conductive material layer in a first plasma chamber with a low cathode temperature, transferring the wafer to a second chamber without breaking vacuum, etching a high-k dielectric layer in the second chamber, and transferring the wafer from the second chamber to the first plasma chamber without breaking vacuum. A lower conductive material layer is etched with a low cathode temperature in the first chamber. In one implementation, the high-k dielectric etch is a plasma etch using a high temperature cathode. In another implementation, the high-k dielectric etch is a reactive ion etch.

    摘要翻译: 在一个实施方式中,提供了能够蚀刻晶片以形成包括高k电介质层的器件的方法。 该方法包括在具有低阴极温度的第一等离子体室中蚀刻上导电材料层,将晶片转移到第二室而不破坏真空,蚀刻第二室中的高k电介质层,以及从第二室转移晶片 室到第一等离子体室,而不破坏真空。 在第一室中以低阴极温度蚀刻下导电材料层。 在一个实施方案中,高k电介质蚀刻是使用高温阴极的等离子体蚀刻。 在另一个实施方案中,高k电介质蚀刻是反应离子蚀刻。