Bipolar Pulse Generators With Voltage Multiplication

    公开(公告)号:US20110266886A1

    公开(公告)日:2011-11-03

    申请号:US13180746

    申请日:2011-07-12

    Inventor: Simon Y. London

    CPC classification number: H04L25/0278 H03K3/53 H03K5/065 H03K5/159 H04B1/7174

    Abstract: A bipolar pulse generator includes two, two-conductor transmission lines coupled together with a load positioned between the two transmission lines. Each conductor of a transmission line we define as a segment. Two segments of one transmission line are charged and switchably coupled to two segments of the other transmission line to produce a bipolar pulse on the matched load. This bipolar pulse generator may be implemented in a flat or a folded design. The generator may include two transmission line structures coupled together with a load positioned between each transmission line structures. The first transmission line structure may include a stepped transmission line and an embedded transmission line segment. A switch may be coupled between the embedded transmission line segment and another segment of the transmission line structure. During operation, the first transmission line structure may be charged to a potential with the switch in the open position and, when the switch is closed, the charge on the first transmission line structure together with the second transmission line structure generates a bipolar pulse on the matched load.

    Bipolar pulse generators with voltage multiplication
    2.
    发明授权
    Bipolar pulse generators with voltage multiplication 有权
    具有电压倍增的双极脉冲发生器

    公开(公告)号:US07986060B2

    公开(公告)日:2011-07-26

    申请号:US12588238

    申请日:2009-10-08

    Inventor: Simon Y. London

    CPC classification number: H04L25/0278 H03K3/53 H03K5/065 H03K5/159 H04B1/7174

    Abstract: A bipolar pulse generator includes two, two-conductor transmission lines coupled together with a load positioned between the two transmission lines. Each conductor of a transmission line we define as a segment. Two segments of one transmission line are charged and switchably coupled to two segments of the other transmission line to produce a bipolar pulse on the matched load. This bipolar pulse generator may be implemented in a flat or a folded design. The generator may include two transmission line structures coupled together with a load positioned between each transmission line structures. The first transmission line structure may include a stepped transmission line and an embedded transmission line segment. A switch may be coupled between the embedded transmission line segment and another segment of the transmission line structure. During operation, the first transmission line structure may be charged to a potential with the switch in the open position and, when the switch is closed, the charge on the first transmission line structure together with the second transmission line structure generates a bipolar pulse on the matched load.

    Abstract translation: 双极性脉冲发生器包括两个双导线传输线,耦合到位于两个传输线之间的负载。 传输线的每个导线我们定义为一段。 一个传输线的两个段被充电并且可切换地耦合到另一个传输线的两个部分,以在匹配的负载上产生双极性脉冲。 该双极性脉冲发生器可以以平面或折叠设计来实现。 发电机可以包括与定位在每个传输线结构之间的负载耦合在一起的两个传输线结构。 第一传输线结构可以包括阶梯式传输线和嵌入式传输线段。 开关可以耦合在嵌入式传输线段和传输线结构的另一段之间。 在操作期间,第一传输线结构可以被充电到开关处于打开位置的电位,并且当开关闭合时,第一传输线结构上的电荷与第二传输线结构一起产生双极性脉冲 匹配负载。

    Method and apparatus for correcting duty cycle error in a clock distribution network
    3.
    发明申请
    Method and apparatus for correcting duty cycle error in a clock distribution network 审中-公开
    用于校正时钟分配网络中的占空比误差的方法和装置

    公开(公告)号:US20070229115A1

    公开(公告)日:2007-10-04

    申请号:US11339124

    申请日:2006-01-25

    CPC classification number: H03K5/1565 G06F1/10 H03K5/065

    Abstract: A clock distribution network for distributing a repetitive timing signal throughout an integrated circuit, the timing signal being within a range of frequencies about a first frequency, includes multiple buffer circuits and at least one conductive segment connecting one of the buffers to another of the buffers. The conductive segment has a length selected so as to be less than a quarter-wave resonance length of the conductive segment at the first frequency to thereby achieve duty cycle correction.

    Abstract translation: 一种用于在整个集成电路中分配重复定时信号的时钟分配网络,定时信号在大约关于第一频率的频率范围内,包括多个缓冲器电路和至少一个将缓冲器之一连接到另一个缓冲器的导电段。 导电段的长度被选择为小于第一频率处的导电段的四分之一波长的谐振长度,从而实现占空比校正。

    RF envelope generator
    4.
    发明授权
    RF envelope generator 失效
    射频包络发生器

    公开(公告)号:US4864258A

    公开(公告)日:1989-09-05

    申请号:US188943

    申请日:1988-05-02

    CPC classification number: H03K5/065 H01P5/12

    Abstract: A microwave rf envelope generator or pulse shaper has a main waveguide with two opposing branches connected in shunt to the main waveguide and are terminated with variable positionable shorts. The characteristic impedance of the shunted combination of the two branches equal one half the characteristic impedance of the main waveguide. An incident rf pulse applied to an input of the main waveguide is transmitted to a four way junction formed at the intersection of the two branches. The incident pulse is divided at the junction. Divided pulses are then transmitted down each of the branches and to an output of the main waveguide. The pulses traveling down each branch will have their phases shifted when they are reflected by the variable positionable shorts. The lengths of the branches are adjusted by the variable shorts so that the phase of the reflected and inverted pulses will cancel the trailing portion of the pulse transmitted out towards the output of the main waveguide. The output pulse width is a function of the time it takes the divided pulses to travel down the branches and back.

    Abstract translation: 微波射频包络发生器或脉冲整形器具有主波导,其中两个相对的分支连接到主波导并联并以可变定位的短路端接。 两个分支的分流组合的特性阻抗等于主波导的特性阻抗的一半。 施加到主波导的输入的入射rf脉冲被传输到形成在两个分支的交叉处的四通接头。 入射脉冲在交界处分开。 然后将分割的脉冲沿着每个分支传送到主波导的输出端。 沿着每个分支行进的脉冲将在它们被可变定位短路反射时相位移动。 通过可变短路来调整分支的长度,使得反射和反相脉冲的相位将抵消朝向主波导的输出发射出的脉冲的尾部。 输出脉冲宽度是分割脉冲沿分支和向后移动所花费的时间的函数。

    Data transmission time domain equalizer
    5.
    发明授权
    Data transmission time domain equalizer 失效
    数据传输时域均衡器

    公开(公告)号:US3577089A

    公开(公告)日:1971-05-04

    申请号:US52079866

    申请日:1966-01-14

    Applicant: IBM

    Inventor: GOROG ETIENNE

    CPC classification number: H04L25/03133 H03K5/065

    Abstract: Apparatus for equalizing digital data which has been distorted in transmission. The value of the signal at each instant of time is delayed and modified by a weighting junction and added to the value of the signal input at the next instant of time in an analog adder. The output of the analog adder is applied to a series of cascaded digital correction devices, the outputs of which are each connected through weighting junctions and switches to the analog adder to control the equalization of the signal input. The equalized signal output is taken from the last of these cascaded correction devices.

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