公开(公告)号：US20150002326A1

公开(公告)日：2015-01-01

申请号：US13928798

申请日：2013-06-27

Applicant: Xilinx, Inc.

Inventor： Brendan Farley ,  James Hudner ,  Ivan Bogue ,  Declan Carey ,  Darragh Walsh ,  Marc Erett

IPC: H03M1/12

CPC classification number: H03M1/12 ,  H03M1/002 ,  H03M1/365

Abstract: An analog-to-digital converter (“ADC”) is disclosed. The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.

Abstract translation: 公开了一种模拟 - 数字转换器（“ADC”）。 ADC包括一组比较器和一个窗口控制器。 窗口控制器耦合到比较器组，以选择性地激活与窗口大小相关联的比较器组的第一比较器，并且选择性地使比较器组的第二比较器失活。

公开(公告)号：US09954539B2

公开(公告)日：2018-04-24

申请号：US15206634

申请日：2016-07-11

Applicant: Xilinx, Inc.

Inventor： Jinyung Namkoong ,  Mayank Raj ,  Parag Upadhyaya ,  Vamshi Manthena ,  Catherine Hearne ,  Marc Erett

IPC: H03L7/06 ,  H03L7/089 ,  H03M9/00

CPC classification number: H03L7/0891 ,  H03L7/0805 ,  H03L7/0995 ,  H03L7/24 ,  H03M9/00

Abstract: A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.

公开(公告)号：US08970419B2

公开(公告)日：2015-03-03

申请号：US13928798

申请日：2013-06-27

Applicant: Xilinx, Inc.

Inventor： Brendan Farley ,  James Hudner ,  Ivan Bogue ,  Declan Carey ,  Darragh Walsh ,  Marc Erett

IPC: H03M1/34 ,  H03M1/12

CPC classification number: H03M1/12 ,  H03M1/002 ,  H03M1/365

Abstract: An analog-to-digital converter (“ADC”). The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.

Abstract translation: 一个模拟 - 数字转换器（“ADC”）。 ADC包括一组比较器和一个窗口控制器。 窗口控制器耦合到比较器组，以选择性地激活与窗口大小相关联的比较器组的第一比较器，并且选择性地使比较器组的第二比较器失活。

公开(公告)号：US20180013435A1

公开(公告)日：2018-01-11

申请号：US15206634

申请日：2016-07-11

Applicant: Xilinx, Inc.

Inventor： Jinyung Namkoong ,  Mayank Raj ,  Parag Upadhyaya ,  Vamshi Manthena ,  Catherine Hearne ,  Marc Erett

IPC: H03L7/089 ,  H03M9/00

CPC classification number: H03L7/0891 ,  H03L7/0805 ,  H03L7/0995 ,  H03L7/24 ,  H03M9/00

Abstract: A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.