-
公开(公告)号：US12124323B2
公开(公告)日：2024-10-22
申请号：US17883379
申请日：2022-08-08
Applicant: XILINX, INC.
Inventor： Ahmad R. Ansari , David P. Schultz , Felix Burton , Jeffrey Cuppett
CPC classification number: G06F11/0763 , G06F9/30101 , G06F11/0772
Abstract: Embodiments herein describe integrity check techniques that are efficient and flexible by using local registers in a segment to store check values which can be used to detect errors in the local configuration data in the same segment. In addition to containing local registers storing the check values, each segment can include a mask register indicated which of the configuration registers should be checked and which can be ignored. Further, the segments can include a next segment register indicating the next segment the check engine should evaluate for errors.
-
2.发明申请公开(公告)号：US20160055106A1
公开(公告)日：2016-02-25
申请号：US14464654
申请日：2014-08-20
Applicant: Xilinx, Inc.
Inventor： Ahmad R. Ansari , Felix Burton
IPC: G06F13/24
CPC classification number: G06F13/24 , G06F9/4812
Abstract: Apparatus and methods for handling inter-processor interrupts (IPIs) in a heterogeneous multiprocessor system are provided. The scalable IPI mechanism provided herein entails minimal logic and can be used for heterogeneous inter-processor communication, such as between application processors, real-time processors, and FPGA accelerators. This mechanism is also low cost, in terms of both logic area and programmable complexity. One example system generally includes a first processor, a second processor being of a different processor type than the first processor, and an IPI circuit. The IPI circuit typically includes a first register associated with the first processor, wherein a first bit in the first register indicates whether the first processor has requested to interrupt the second processor; and a second register associated with the second processor, wherein a second bit in the second register indicates whether the second processor has requested to interrupt the first processor.
Abstract translation: 提供了用于处理异构多处理器系统中的处理器间中断（IPI）的设备和方法。 这里提供的可扩展IPI机制需要最小的逻辑，并且可以用于异构处理器间通信，例如应用处理器，实时处理器和FPGA加速器之间。 这种机制在逻辑区域和可编程复杂性方面也是低成本的。 一个示例系统通常包括第一处理器，与第一处理器不同的处理器类型的第二处理器和IPI电路。 IPI电路通常包括与第一处理器相关联的第一寄存器，其中第一寄存器中的第一位指示第一处理器是否请求中断第二处理器; 以及与第二处理器相关联的第二寄存器，其中第二寄存器中的第二位指示第二处理器是否请求中断第一处理器。
-
公开(公告)号：US10896119B1
公开(公告)日：2021-01-19
申请号：US16180811
申请日：2018-11-05
Applicant: Xilinx, Inc.
Inventor： Ahmad R. Ansari , Felix Burton , Henry C. Yu
Abstract: An input-output circuit is coupled to a plurality of serial communication paths and to a physical point-to-point interface. The input-output circuit is configured to transmit data received on the plurality of serial communication paths over the physical point-to-point interface. An application circuit is coupled to the input-output circuit and is configured to communicate via a first one of the paths in performing application functions. A bridge circuit is coupled to the input-output circuit and is configured to communicate via a second one of the paths. A debug circuit is coupled to the application circuit and to the bridge circuit. The debug circuit is configured to capture debug data of the application circuit and provide the debug data to the bridge circuit for communication via the second one of the paths.
-
Patent Agency Ranking
公开(公告)号：US20190303268A1
公开(公告)日：2019-10-03
申请号：US15944137
申请日：2018-04-03
Applicant: Xilinx,Inc.
Inventor： Ahmad R. Ansari , Felix Burton , Ming-dong Chen
IPC: G06F11/36 , G01R31/317 , G06F17/50
Abstract: A circuit arrangement includes one or more input buffers disposed on a system-on-chip (SoC) and configured to receive and store streaming debug packets. One or more response buffers are also disposed on the SoC. A transaction control circuit is disposed on the SoC and is configured to process each debug packet in the one or more input buffers. The processing includes decoding an operation code in the debug packet, and determining from an address in the debug packet, an interface circuit of multiple interface circuits to access a storage circuit in a subsystem of multiple sub-systems on the SoC. The processing further includes issuing a request via the interface circuit to access the storage circuit according to the operation code, and storing responses and data received from the interface circuits in the one or more response buffers.
-
公开(公告)号：US12020021B2
公开(公告)日：2024-06-25
申请号：US17839265
申请日：2022-06-13
Applicant: XILINX, INC.
Inventor： Ahmad R. Ansari , Felix Burton
IPC: G06F8/656 , G06F9/4401 , G06F9/445 , G06F21/57
CPC classification number: G06F8/656 , G06F9/4401 , G06F9/445 , G06F21/572 , G06F2221/033
Abstract: Techniques to update firmware without a system reset include preserving state information associated with one or more firmware services, suspending processing of firmware service requests, loading an updated firmware image, and resuming processing of firmware service requests based on the preserved state information and the updated firmware image. Unpreserved states of one or more other firmware services may be recreated upon resumption of processing of the firmware service requests.
-
公开(公告)号：US11216591B1
公开(公告)日：2022-01-04
申请号：US16439350
申请日：2019-06-12
Applicant: Xilinx, Inc.
Inventor： Felix Burton , Krishna C. Patakamuri , James D. Wesselkamper
Abstract: Apparatus and associated methods relate to authenticating a back-to-front-built configuration image. In an illustrative example, a circuit may include memory configured to store a signature S, a second hash H2, and a first data chunk C1. Signature S may be signed on a first hash H1. H1 may be the hash for H2 and C1. If signature S passes verification, a hash engine may perform hash functions on C1 and H2 to generate a hash H1′. H1′ may be compared with H1 to indicate whether C1 has been tampered with or not. By using the incremental authentication, a signature that appears at the beginning of the image may be extended to the entire image while only using a small internal buffer. Advantageously, internal buffer may only need to store two hashes Hi, Hi+1, and a data chunk Ci, or, a signature S, a hash Hi, and a data chunk Ci.
-
公开(公告)号：US10789153B2
公开(公告)日：2020-09-29
申请号：US15944137
申请日：2018-04-03
Applicant: Xilinx, Inc.
Inventor： Ahmad R. Ansari , Felix Burton , Ming-dong Chen
IPC: G06F11/00 , G06F11/36 , G01R31/317 , G01R31/3185 , G06F11/22 , G06F11/267 , G06F11/273 , G06F30/34
Abstract: A circuit arrangement includes one or more input buffers disposed on a system-on-chip (SoC) and configured to receive and store streaming debug packets. One or more response buffers are also disposed on the SoC. A transaction control circuit is disposed on the SoC and is configured to process each debug packet in the one or more input buffers. The processing includes decoding an operation code in the debug packet, and determining from an address in the debug packet, an interface circuit of multiple interface circuits to access a storage circuit in a subsystem of multiple sub-systems on the SoC. The processing further includes issuing a request via the interface circuit to access the storage circuit according to the operation code, and storing responses and data received from the interface circuits in the one or more response buffers.
-
公开(公告)号：US09665509B2
公开(公告)日：2017-05-30
申请号：US14464654
申请日：2014-08-20
Applicant: Xilinx, Inc.
Inventor： Ahmad R. Ansari , Felix Burton
CPC classification number: G06F13/24 , G06F9/4812
Abstract: Apparatus and methods for handling inter-processor interrupts (IPIs) in a heterogeneous multiprocessor system are provided. The scalable IPI mechanism provided herein entails minimal logic and can be used for heterogeneous inter-processor communication, such as between application processors, real-time processors, and FPGA accelerators. This mechanism is also low cost, in terms of both logic area and programmable complexity. One example system generally includes a first processor, a second processor being of a different processor type than the first processor, and an IPI circuit. The IPI circuit typically includes a first register associated with the first processor, wherein a first bit in the first register indicates whether the first processor has requested to interrupt the second processor; and a second register associated with the second processor, wherein a second bit in the second register indicates whether the second processor has requested to interrupt the first processor.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.013 seconds)
