公开(公告)号：US20250130770A1

公开(公告)日：2025-04-24

申请号：US18493233

申请日：2023-10-24

Applicant: Xilinx, Inc.

Inventor： Chinmaya Dash

IPC: G06F7/523 ,  G06F5/01 ,  G06F7/50 ,  H03K19/21

Abstract: An implementation may include a method for performing a binary multiplication including receiving a first at an input interface of a digital multiplier circuit in the computing system, receiving a second operand at the input interface of the digital multiplier circuit, generating, by the digital multiplier circuit, partial products by performing a AND operation with each of the N bits of the first operand and each of the bits of the second operand, and generating first modified partial products by modifying, by the digital multiplier circuit, most significant bits of the partial products, generating second modified partial products by modifying, by the digital multiplier circuit, one of the first modified partial product, generating, by the digital multiplier circuit, a product by summing the second modified partial products, and outputting the product from an output interface of the digital multiplier circuit.

公开(公告)号：US20250124204A1

公开(公告)日：2025-04-17

申请号：US18381052

申请日：2023-10-17

Applicant: XILINX, INC.

Inventor： Pawan KULSHRESHTHA ,  Atul SRINIVASAN

IPC: G06F30/3312 ,  G06F30/31

Abstract: Performing timing analysis of a circuit design includes building a timing graph of the circuit design, and determining delays of devices and wires of the circuit design based on the timing graph. Further, clock and arrival propagations for the circuit design are performed based on the delays of the devices and wires, latch loops are identified in the circuit design, and latch analysis on latches of the latch loops is performed. The timing analysis further includes performing arrival propagation for circuit elements of the circuit design impacted by the latch analysis performed on the latches of the latch loops, performing latch analysis on latches of the circuit design external to the latch loops, and performing required time and slack calculations on the circuit design.

公开(公告)号：US20250079276A1

公开(公告)日：2025-03-06

申请号：US18241140

申请日：2023-08-31

Applicant: Advanced Micro Devices, Inc. ,  XILINX, INC.

Inventor： Manish DUBEY ,  Frank Peter LAMBRECHT ,  Brett P. WILKERSON ,  Deepak Vasant KULKARNI ,  Hemanth Kumar DHAVALESWARAPU ,  Priyal SHAH

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/043 ,  H01L25/065 ,  H05K1/14

Abstract: Disclosed herein is a chip package assembly that includes a package substrate coupled with an integrated circuit die, a stiffener attached to a top surface of the package substrate, and a connector assembly integrated with the stiffener. Both the connector assembly and the stiffener are disposed at a peripheral area of the top surface. The connector assembly includes a bracket and a connector. The connector is configured to connect with one or more optical cables or electrical connectors. The bracket may be formed by a cavity in the stiffener. The bracket may be attached to the top surface of the package substrate. The stiffener may be coupled with the bracket directly or via the connector. Additionally, a frame coupled to the stiffener or a PCB board may be used to secure the bracket in place.

公开(公告)号：US20250077243A1

公开(公告)日：2025-03-06

申请号：US18242246

申请日：2023-09-05

Applicant: XILINX, INC.

Inventor： Mohan Marutirao DHANAWADE ,  Ramakrishna Ganeshu POOLLA ,  Ahmad R. ANSARI

IPC: G06F9/448

Abstract: Some examples described herein provide for instruction glitch protection in an integrated circuit. In an example, a method includes generating a random number by the integrated circuit. The method also includes identifying, based at least in part on the generated random number, a sequence from a set of sequences stored in a memory of the integrated circuit, each sequence of the set of sequences corresponding to an order of execution for a plurality of tasks. The method further includes performing, by the integrated circuit, each task of the plurality of tasks in the order of execution corresponding to the identified sequence.

公开(公告)号：US20250069579A1

公开(公告)日：2025-02-27

申请号：US18236221

申请日：2023-08-21

Applicant: Advanced Micro Devices, Inc. ,  XILINX, INC.

Inventor： Gamal REFAI-AHMED ,  Christopher JAGGERS ,  Hoa DO ,  Md Malekkul ISLAM ,  Paul Theodore ARTMAN ,  Sukesh SHENOY ,  Suresh RAMALINGAM ,  Muhammad Afiq Bin In BAHAROM

IPC: G10K11/178

Abstract: In one example, a micro device includes a housing; a chip package disposed in the housing; a noise producing component coupled to the housing. The micro device also includes a noise reduction system having a reference microphone for detecting a noise from the noise producing component and a controller configured to receive the noise from the reference microphone and generate a masking sound signal in response to the detected noise. A speaker is coupled to the housing for producing a masking sound corresponding to the masking sound signal, whereby the masking sound reduces the noise. In another example, the noise producing component comprises a fan.

公开(公告)号：US20250061926A1

公开(公告)日：2025-02-20

申请号：US18235739

申请日：2023-08-18

Applicant: XILINX, INC.

Inventor： Santosh YACHARENI ,  Sree Rama Krishna Chaithnya SARASWATULA ,  Shidong ZHOU ,  Anil Kumar KANDALA ,  Narendra Kumar PULIPATI

IPC: G11C7/08 ,  G11C7/10 ,  G11C7/20

Abstract: Memory driver circuitry for driving a memory cell or cells of a memory device includes first driver path circuitry and selection circuitry. The first driver path circuitry includes driver circuitry that outputs a first signal and selection circuitry that receives the first signal and a second signal, and outputs a first selected signal. The first selected signal is a selected one of the first signal and the second signal. The selection circuitry of the memory driver circuitry receives a third signal and a fourth signal, and outputs a bias voltage signal to header circuitry of a memory cell. The bias voltage signal is a selected one of the third signal and the fourth signal. The third signal corresponds to the first selected signal.

公开(公告)号：US12223355B2

公开(公告)日：2025-02-11

申请号：US17455074

申请日：2021-11-16

Applicant: Xilinx, Inc.

Inventor： Karthik Shankar ,  Jaideep Dastidar ,  Ahmad R. Ansari ,  Sagheer Ahmad

IPC: G06F9/44 ,  G06F9/50

Abstract: Synchronizing system resources of a multi-socket data processing system can include providing, from a primary System-on-Chip (SOC), a trigger event to a global synchronization circuit. The primary SOC is one of a plurality of SOCS and the trigger event is provided over a first sideband channel. In response to the trigger event, the global synchronization circuit is capable of broadcasting a synchronization event to the plurality of SOCS over a second sideband channel. In response to the synchronization event, the system resource of each SOC of the plurality of SOCS is programmed with a common value. The programming synchronizes the system resources of the plurality of SOCS.

公开(公告)号：US20250047285A1

公开(公告)日：2025-02-06

申请号：US18229152

申请日：2023-08-01

Applicant: XILINX, INC.

Inventor： Lakshmi Venkata Satya Lalitha Indumathi JANASWAMY ,  Narendra Kumar PULIPATI ,  Shidong ZHOU ,  Anil Kumar KANDALA ,  Santosh YACHARENI ,  Sree Rama Krishna Chaithnya SARASWATULA

IPC: H03K19/0185 ,  H03K3/037

Abstract: A level shifter may include a first transistor stack including at least four transistors arranged from a first voltage source to ground, including second and third transistors coupled with bias voltage source, and a fourth transistor coupled with an input to receive an input signal at a second voltage or ground. The level shifter may include a second transistor stack comprising at least four transistors arranged from the first voltage source to ground, including second and third transistors coupled with the bias voltage source, and a fourth transistor to receive an inverse of the input signal. A first transistor of the first transistor stack is cross-coupled with a first transistor of the second transistor stack. A level shifter may include a first output coupled with the second transistor stack between the second and third transistors to provide a first output signal at the first voltage or ground.

公开(公告)号：US12191876B2

公开(公告)日：2025-01-07

申请号：US18088982

申请日：2022-12-27

Applicant: Xilinx, Inc.

Inventor： Bob Verbruggen ,  Christophe Erdmann

IPC: H03M1/10

Abstract: Methods and apparatus for calibrating a gain for a circuit block are disclosed. An example method includes receiving a plurality of quantizer offsets, where the plurality of quantizer offsets represent calibration data for a quantizer configured to quantize an output of the circuit block, determining one or more differences based on one or more first quantizer offsets of the plurality of quantizer offsets and on one or more second quantizer offsets of the plurality of quantizer offsets, and determining an incremental change in a gain associated with the circuit block based on the one or more differences.

公开(公告)号：US12190994B2

公开(公告)日：2025-01-07

申请号：US18090574

申请日：2022-12-29

Applicant: XILINX, INC.

Inventor： Kumar Rahul ,  Santosh Yachareni ,  Mahendrakumar Gunasekaran ,  Mohammad Anees

IPC: G11C7/22 ,  G11C7/10

Abstract: An integrated circuitry (IC) device for a memory device includes driver circuitry, selection circuitry, clock generation circuitry, and self-time path circuitry. The driver circuitry generates a plurality of driver circuitry outputs. The selection circuitry selects one of the plurality of driver circuitry outputs based on a plurality of enable signals. The clock generation circuitry receives the selected one of the plurality of driver circuitry outputs from the selection circuitry, and generates a clock signal based on at least the selected one of the plurality of driver circuitry outputs from the selection circuitry. The self-time path circuitry of a memory receives the clock signal and generates a reset signal based on the clock signal. The plurality of driver circuitry outputs and the clock signal are based on the reset signal, and the self-time path circuitry corresponds to one or more columns of a memory bank.