公开(公告)号：US11003826B1

公开(公告)日：2021-05-11

申请号：US16397501

申请日：2019-04-29

Applicant: Xilinx, Inc.

Inventor： Srinivasan Dasasathyan ,  Padmini Gopalakrishnan ,  Vishal Tripathy ,  Vikas N. Vedamurthy ,  Sumit Nagpal

IPC: G06F30/392 ,  G06F30/327 ,  G06F111/04

Abstract: Strategies are stored in a memory arrangement, and each strategy includes a set of parameter settings for a design tool. The design tool identifies a set of features of an input circuit design and applies classification models to the input circuit design. Each classification model indicates one the strategies, and application of each classification model indicates a likelihood that use of the strategy would improve a metric of the input circuit design based on the set of features of the input circuit design. One strategy of the plurality of strategies is selected based on the likelihood that use of the one strategy would improve the metric of the input circuit design, and the design tool is configured with the set of parameter settings of the one strategy. The design tool then processes the input circuit design into implementation data that is suitable for making an integrated circuit (IC).

公开(公告)号：US11586791B1

公开(公告)日：2023-02-21

申请号：US17480389

申请日：2021-09-21

Applicant: Xilinx, Inc.

Inventor： Anup Hosangadi ,  Aman Gayasen ,  Srinivasan Dasasathyan ,  Padmini Gopalakrishnan

IPC: G06F30/31 ,  G06F30/394

Abstract: Approaches for visualizing data buses in a circuit design include determining ones of the data buses that satisfy selection criteria. For each element connected to a data bus of the ones of the data buses, a method and system determine whether the element is of interest or the element is not of interest. A graphical representation of the ones of the data buses and each element of interest is generated, and data buses of the circuit design determined to not satisfy the selection criteria and elements not of interest are excluded from the graphical representation. The graphical representation is displayed on a display device.

公开(公告)号：US20240211675A1

公开(公告)日：2024-06-27

申请号：US18145704

申请日：2022-12-22

Applicant: Xilinx, Inc.

Inventor： Mohammed Bader Alam ,  Goutham Pocklassery ,  Ravishankar Menon ,  Sumit Nagpal ,  Mahesh Suresh Mahadurkar ,  Padmini Gopalakrishnan

IPC: G06F30/394 ,  G06F30/392

CPC classification number: G06F30/394 ,  G06F30/392

Abstract: A design for a programmable integrated circuit (IC) is synthesized and includes an inference engine and a data transformer. A portion of the design including the data transformer is designated as a dynamic function exchange (DFX) module. The inference engine is excluded from the DFX module. The design is implemented, by placing and routing, such that the DFX module is confined to a defined physical area of the programmable integrated circuit. An abstract shell for the design specifying boundary connections of the DFX module as placed and routed is generated. A locked version of the design as placed and routed with the DFX module removed is generated. The method includes implementing a different data transformer as a further DFX module for the design using the abstract shell.

公开(公告)号：US11714950B2

公开(公告)日：2023-08-01

申请号：US17382621

申请日：2021-07-22

Applicant: Xilinx, Inc.

Inventor： Veeresh Pratap Singh ,  Meghraj Kalase ,  John Blaine ,  Srinivasan Dasasathyan ,  Padmini Gopalakrishnan ,  Frederic Revenu ,  Veena Johar ,  Pawan Kumar Singh ,  Mohit Sharma ,  Kameshwar Chandrasekar

IPC: G06F30/392 ,  G06F30/398 ,  G06F30/327 ,  G06F30/31

CPC classification number: G06F30/398 ,  G06F30/31 ,  G06F30/327 ,  G06F30/392

Abstract: Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected. The selected implementation is iteratively optimized to satisfy the timing requirement, while restricting changes to placement of cells and nets on a critical path of the one implementation to less than a threshold portion of cells and nets on the critical path.

公开(公告)号：US20230034736A1

公开(公告)日：2023-02-02

申请号：US17382621

申请日：2021-07-22

Applicant: Xilinx, Inc.

Inventor： Veeresh Pratap Singh ,  Meghraj Kalase ,  John Blaine ,  Srinivasan Dasasathyan ,  Padmini Gopalakrishnan ,  Frederic Revenu ,  Veena Johar ,  Pawan Kumar Singh ,  Mohit Sharma ,  Kameshwar Chandrasekar

IPC: G06F30/398 ,  G06F30/31 ,  G06F30/327 ,  G06F30/392

Abstract: Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected. The selected implementation is iteratively optimized to satisfy the timing requirement, while restricting changes to placement of cells and nets on a critical path of the one implementation to less than a threshold portion of cells and nets on the critical path.