公开(公告)号：US20140252599A1

公开(公告)日：2014-09-11

申请号：US13791819

申请日：2013-03-08

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam ,  Namhoon Kim ,  Joong-Ho Kim

IPC: H01L21/768 ,  H01L23/498

CPC classification number: H01L21/76802 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H05K3/28 ,  H05K3/4682

Abstract: A substrate-less interposer for a stacked silicon interconnect technology (SSIT) product, includes: a plurality of metallization layers, at least a bottom most layer of the metallization layers comprising a plurality of metal segments, wherein each of the plurality of metal segments is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers, and the metal segments are separated by dielectric material in the bottom most layer; and a dielectric layer formed on the bottom surface of the bottom most layer, wherein the dielectric layer includes one or more openings for providing contact to the plurality of metal segments in the bottom most layer.

Abstract translation: 一种用于层叠硅互连技术（SSIT）产品的无衬底插入件包括：多个金属化层，至少最底层的金属化层包括多个金属段，其中多个金属段中的每一个均为 形成在金属化层的最底层的顶表面和底表面之间，并且金属段由最底层中的电介质材料分离; 以及形成在最底层的底表面上的电介质层，其中介电层包括用于提供与最底层中的多个金属段接触的一个或多个开口。

公开(公告)号：US08946884B2

公开(公告)日：2015-02-03

申请号：US13791819

申请日：2013-03-08

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam ,  Namhoon Kim ,  Joong-Ho Kim

IPC: H01L23/12 ,  H01L23/48 ,  H01L23/485 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H05K3/28 ,  H05K3/46 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L21/76802 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H05K3/28 ,  H05K3/4682

Abstract: A substrate-less interposer for a stacked silicon interconnect technology (SSIT) product, includes: a plurality of metallization layers, at least a bottom most layer of the metallization layers comprising a plurality of metal segments, wherein each of the plurality of metal segments is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers, and the metal segments are separated by dielectric material in the bottom most layer; and a dielectric layer formed on the bottom surface of the bottom most layer, wherein the dielectric layer includes one or more openings for providing contact to the plurality of metal segments in the bottom most layer.

Abstract translation: 一种用于层叠硅互连技术（SSIT）产品的无衬底插入件包括：多个金属化层，至少最底层的金属化层包括多个金属段，其中多个金属段中的每一个均为 形成在金属化层的最底层的顶表面和底表面之间，并且金属段由最底层中的电介质材料分离; 以及形成在最底层的底表面上的电介质层，其中介电层包括用于提供与最底层中的多个金属段接触的一个或多个开口。

公开(公告)号：US20140262440A1

公开(公告)日：2014-09-18

申请号：US13827048

申请日：2013-03-14

Applicant: Xilinx, Inc.

Inventor： Namhoon Kim ,  Joong-Ho Kim ,  Suresh Ramalingam ,  Paul Y. Wu ,  Woon-Seong Kwon ,  Dennis C.P. Leung

IPC: H05K1/02

CPC classification number: H05K1/02 ,  H01L23/49822 ,  H01L23/66 ,  H01L2224/16225

Abstract: A multi-layer core organic package substrate includes: a multi-layer core comprising at least two organic core layers, wherein two of the at least two organic core layers are separated by a core metal layer; a first plurality of build-up layers formed on top of the multi-core layer; and a second plurality of build-up layers formed below the multi-core layer.

Abstract translation: 多层核心有机封装基板包括：包含至少两个有机芯层的多层芯，其中所述至少两个有机芯层中的两个被芯金属层分隔开; 形成在所述多芯层的顶部上的第一多个堆积层; 以及形成在所述多芯层下方的第二多个积聚层。