公开(公告)号：US20140091819A1

公开(公告)日：2014-04-03

申请号：US13630215

申请日：2012-09-28

Applicant: XILINX, INC.

Inventor： Yuqing Gong ,  Henley Liu ,  Myongseob Kim ,  Suresh P. Parameswaran ,  Cheang-Whang Chang ,  Boon Y. Ang

IPC: G01R31/3187

CPC classification number: G01R31/31926 ,  G01R31/2812 ,  G01R31/31717 ,  G01R31/31723 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: An integrated circuit (IC) comprises routing circuitry including a plurality of signal line segments in routing layers of the IC, and a plurality of micro-bump contacts coupled to the routing circuitry. The IC includes a plurality of test circuits coupled to respective subsets of the plurality of signal line segments. Each test circuit is configured to connect micro-bump contacts in the respective subset to form first and second sets of daisy chains. Each test circuit is configured to test the first and second sets of daisy chains for open circuits and test for short circuits between the first and second sets of daisy chains. Each test circuit is configured to determine the locations of detected open circuits and determine the locations of detected short circuits.

Abstract translation: 集成电路（IC）包括路由电路，其包括在IC的路由层中的多个信号线段以及耦合到路由电路的多个微突点接触。 IC包括耦合到多个信号线段的相应子集的多个测试电路。 每个测试电路被配置为连接相应子集中的微凸块触点以形成第一组和第二组菊花链。 每个测试电路被配置为测试用于开路的第一和第二组菊花链，并测试第一组和第二组菊花链之间的短路。 每个测试电路被配置为确定检测到的开路的位置并确定检测到的短路的位置。

公开(公告)号：US08810269B2

公开(公告)日：2014-08-19

申请号：US13630215

申请日：2012-09-28

Applicant: Xilinx, Inc.

Inventor： Yuqing Gong ,  Henley Liu ,  Myongseob Kim ,  Suresh P. Parameswaran ,  Cheang-Whang Chang ,  Boon Y. Ang

IPC: G01R31/3187

CPC classification number: G01R31/31926 ,  G01R31/2812 ,  G01R31/31717 ,  G01R31/31723 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: An integrated circuit (IC) comprises routing circuitry including a plurality of signal line segments in routing layers of the IC, and a plurality of micro-bump contacts coupled to the routing circuitry. The IC includes a plurality of test circuits coupled to respective subsets of the plurality of signal line segments. Each test circuit is configured to connect micro-bump contacts in the respective subset to form first and second sets of daisy chains. Each test circuit is configured to test the first and second sets of daisy chains for open circuits and test for short circuits between the first and second sets of daisy chains. Each test circuit is configured to determine the locations of detected open circuits and determine the locations of detected short circuits.

Abstract translation: 集成电路（IC）包括路由电路，其包括在IC的路由层中的多个信号线段以及耦合到路由电路的多个微突点接触。 IC包括耦合到多个信号线段的相应子集的多个测试电路。 每个测试电路被配置为连接相应子集中的微凸块触点以形成第一组和第二组菊花链。 每个测试电路被配置为测试用于开路的第一和第二组菊花链，并测试第一组和第二组菊花链之间的短路。 每个测试电路被配置为确定检测到的开路的位置并确定检测到的短路的位置。

公开(公告)号：US10262911B1

公开(公告)日：2019-04-16

申请号：US15379258

申请日：2016-12-14

Applicant: Xilinx, Inc.

Inventor： Yuqing Gong ,  Henley Liu ,  Myongseob Kim ,  Suresh P. Parameswaran ,  Cheang-Whang Chang ,  Boon Y. Ang

IPC: H01L21/66 ,  H01L23/00

Abstract: A circuit for testing bond connections between a first die and a second die is described. The circuit comprises a defect monitoring circuit implemented on the first die, which is configured as a test die; and a plurality of bond connections between the first die and the second die; wherein the defect monitoring circuit is configured to detect a defect in a bond connection of the plurality of bond connections between the first die and the second die. A method of testing bond connections between a first die and a second die is also described.

公开(公告)号：US11073550B1

公开(公告)日：2021-07-27

申请号：US16398012

申请日：2019-04-29

Applicant: Xilinx, Inc.

Inventor： Yuqing Gong ,  Suresh Parameswaran ,  Boon Y. Ang

IPC: G01R31/28 ,  G01R31/50 ,  G01R31/71

Abstract: A test vehicle, along with methods for fabricating and using a test vehicle, are disclosed herein. In one example, a test vehicle is provided that includes a substrate, at least a first passive die mounted on the substrate, and at least a first test die mounted on the substrate. The first test die includes test circuitry configured to test continuity through solder interconnects formed between the substrate and the first passive die.