Error correction system using an iterative product code
    1.
    发明授权
    Error correction system using an iterative product code 有权
    纠错系统使用迭代产品代码

    公开(公告)号:US09048879B1

    公开(公告)日:2015-06-02

    申请号:US13586710

    申请日:2012-08-15

    IPC分类号: H03M13/29 H04L1/00

    摘要: An error correction system includes an iterative code that employs an interleaved component code and an embedded parity component code. In some embodiments, on the transmission side, input signals received at an input node are encoded based on the interleaved code, which encodes an interleaved version of the input data to produce a first set of codewords. At least a portion of the first set of codewords preferably is divided into a plurality of symbols which are encoded based on the embedded parity code to provide encoded data. Similarly, in some embodiments, on the receiving side, received data are detected to produce detected information and soft outputs. The detected information is decoded based on the embedded parity code to obtain decoded information. The decoded information preferably is used, together with other soft information, by an interleaved decoder to generate reliability metrics for biasing a subsequent decoding iteration.

    摘要翻译: 纠错系统包括使用交织分量代码和嵌入奇偶校验分量代码的迭代代码。 在一些实施例中,在传输侧,在输入节点处接收的输入信号基于交织的代码进行编码,该代码编码输入数据的交错版本以产生第一组码字。 第一组码字的至少一部分优选地被划分为多个符号,这些符号基于嵌入的奇偶校验码被编码以提供编码数据。 类似地,在一些实施例中,在接收侧,检测所接收的数据以产生检测到的信息和软输出。 检测到的信息根据嵌入的奇偶校验码进行解码以获得解码的信息。 解码的信息优选地与其他软信息一起被交织的解码器使用以产生用于偏置随后的解码迭代的可靠性度量。

    Group based read reference voltage management in flash memory
    2.
    发明授权
    Group based read reference voltage management in flash memory 有权
    闪存中基于组的读参考电压管理

    公开(公告)号:US08363478B1

    公开(公告)日:2013-01-29

    申请号:US13017430

    申请日:2011-01-31

    IPC分类号: G11C11/34 G11C6/04

    摘要: Apparatuses, methods, and other embodiments associated with group based read reference voltage management in flash memory are described. According to one embodiment, an apparatus includes an interval logic configured to create a finite set of timer intervals, a partition logic configured to selectively assign a Vref value to a set of flash memory cells as a function of a given timer interval during which the set of flash memory cells are programmed, and an adaptation logic configured to selectively adapt a given Vref value associated with a flash memory cell upon determining that the flash memory cell has been read.

    摘要翻译: 描述了与闪存中的基于组的读取参考电压管理相关联的装置,方法和其它实施例。 根据一个实施例,一种装置包括间隔逻辑,其被配置为创建有限的一组定时器间隔,分区逻辑被配置为根据给定的定时器间隔来选择性地将一个Vref值分配给一组闪存单元, 闪存单元被编程,并且适配逻辑被配置为在确定闪存单元已经被读取之后选择性地调整与闪存单元相关联的给定Vref值。

    Determining threshold voltage distribution in flash memory
    3.
    发明授权
    Determining threshold voltage distribution in flash memory 有权
    确定闪存中的阈值电压分布

    公开(公告)号:US08331169B1

    公开(公告)日:2012-12-11

    申请号:US13323787

    申请日:2011-12-12

    IPC分类号: G11C7/00

    摘要: Methods, apparatuses, and systems for comparing threshold voltages of a plurality of flash memory cells to a plurality of reference voltages. A number of flash memory cells having threshold voltages that fall within each bin of a plurality of bins is determined. The plurality of bins each represent a plurality of threshold voltage ranges. A threshold voltage distribution of the plurality of flash memory cells is calculated based at least in part on the number of flash memory cells that fall into each of the bins.

    摘要翻译: 用于将多个快闪存储器单元的阈值电压与多个参考电压进行比较的方法,装置和系统。 确定具有落在多个箱体的每个箱体内的阈值电压的多个闪存单元。 多个箱体各自表示多个阈值电压范围。 至少部分地基于落入每个仓的闪存单元的数量来计算多个快闪存储单元的阈值电压分布。

    Decoding methods and apparatus for fractional multidimensional trellis coded modulation systems
    4.
    发明授权
    Decoding methods and apparatus for fractional multidimensional trellis coded modulation systems 有权
    用于分数多维网格编码调制系统的解码方法和装置

    公开(公告)号:US08176401B1

    公开(公告)日:2012-05-08

    申请号:US12021951

    申请日:2008-01-29

    IPC分类号: H03M13/03

    摘要: Systems and methods for encoding user information and decoding signal vectors using fractional encoding/decoding and set partitioning. A fractional encoder can select a coset for transmitting or storing user information based on one or more deterministic bits and on encoded user information. The deterministic bits limit the encoder to using only a subset of the available signal vectors in a modulation scheme. A fractional decoder can receive a signal vector, and can find at least two nearest neighbors in each dimension. The fractional decoder can form a set of potential signal vectors using only the at least two nearest neighbors. The decoder may determine which of these potential signal vectors are valid within the fractional signaling scheme, and can decode the received signal vector based on the valid potential signal vectors.

    摘要翻译: 用于编码用户信息的系统和方法,并使用分数编码/解码和设置分区对信号向量进行解码。 分数编码器可以基于一个或多个确定性位和编码的用户信息来选择用于发送或存储用户信息的陪集。 确定性位将编码器限制为在调制方案中仅使用可用信号向量的子集。 分数解码器可以接收信号向量,并且可以在每个维度中找到至少两个最近的邻居。 分数解码器可以仅使用至少两个最近的邻居形成一组潜在的信号向量。 解码器可以在分数信令方案中确定这些潜在信号向量中的哪一个是有效的,并且可以基于有效的电位信号向量对接收的信号向量进行解码。

    Detecting insertion/deletion using LDPC code
    6.
    发明授权
    Detecting insertion/deletion using LDPC code 有权
    使用LDPC码检测插入/删除

    公开(公告)号:US08812929B1

    公开(公告)日:2014-08-19

    申请号:US13443411

    申请日:2012-04-10

    IPC分类号: G06F11/00

    摘要: Systems and methods are provided that use LDPC codes to determine the locations of insertions or deletions within bit-strings of information transmitted through communication channels and which notify a LDPC decoder of the locations of the insertions or deletions prior to the start of the decoding process. The use of such systems and methods, according to this disclosure, may improve LDPC decoder performance by reducing errors cause by insertions and/or deletions. The use of such systems and methods, according to this disclosure, may also provide improved application performance and larger data transmission rates.

    摘要翻译: 提供了使用LDPC码来确定在通过通信信道发送的信息的位串内的插入或删除的位置并且在解码过程开始之前通知LDPC解码器插入或删除的位置的系统和方法。 根据本公开,使用这样的系统和方法可以通过减少由插入和/或删除引起的错误来改善LDPC解码器性能。 根据本公开的这样的系统和方法的使用也可以提供改进的应用性能和更大的数据传输速率。

    Systems and methods for generating soft information in NAND flash
    7.
    发明授权
    Systems and methods for generating soft information in NAND flash 有权
    用于在NAND闪存中生成软信息的系统和方法

    公开(公告)号:US08681564B2

    公开(公告)日:2014-03-25

    申请号:US13477678

    申请日:2012-05-22

    IPC分类号: G11C16/00

    摘要: Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an applied reference signal is measured. The applied reference signal includes a voltage value and position information. A single bin is identified based on the position information of the reference signal. The identified bin is split into more than one bin based on the output of the memory cell and the voltage value of the reference signal. The newly split bins and all the other bins that were not split are assigned new bin indices.

    摘要翻译: 提供系统和方法以产生与存储器单元的阈值电压相关的软信息。 用于存储器单元的阈值电压的范围被划分为这里称为仓的阈值电压值的子区域。 测量响应于所施加的参考信号的存储单元的输出。 所施加的参考信号包括电压值和位置信息。 基于参考信号的位置信息来识别单个箱。 基于存储单元的输出和参考信号的电压值,将识别的箱分成多于一个箱。 新拆分的箱体以及未分割的所有其他箱体被分配新的箱子索引。

    Systems and methods for multistage error correction

    公开(公告)号:US08495458B1

    公开(公告)日:2013-07-23

    申请号:US12619353

    申请日:2009-11-16

    IPC分类号: G06F11/00

    摘要: In one embodiment, the present invention includes an error correction method. The error correction method comprises receiving a digital signal and processing the digital signal to perform a first error correction. The first error correction includes a first correction for data insertions or deletions and a first correction of data errors to generate a reference signal. The reference signal corresponds to the digital signal having been corrected to a first correction accuracy. The digital signal and the reference signal may be processed to perform a second correction for data insertions or deletions to generate a synchronized signal. The second correction of the digital signal is based on the reference signal, and the correction accuracy of the second correction is more accurate than the first correction accuracy.

    Systems and methods for encoding data to meet an output constraint
    9.
    发明授权
    Systems and methods for encoding data to meet an output constraint 有权
    用于编码数据以满足输出约束的系统和方法

    公开(公告)号:US08418031B1

    公开(公告)日:2013-04-09

    申请号:US12701895

    申请日:2010-02-08

    IPC分类号: H03M13/00

    摘要: In a method of encoding data, a data block is received; transformed, error-corrected encoded data blocks based on the received data block are generated and one is selected based on a constraint; and the selected data block is transmitted. The method may include adding, to the received data block, pivot data corresponding to different transformations. In an apparatus, an encoded data generator is configured to generate different encoded data block candidates based on a received data block, and a selector is configured to select one of the candidates to output as encoded data based on a constraint. The encoded data generator may include a transformer configured to apply one or more transformations to the received data block, and an error correction code (ECC) encoder configured to apply error correction to the received data block. The encoded data generator and the selector may be included in a transmitter.

    摘要翻译: 在编码数据的方法中,接收数据块; 生成基于接收到的数据块的经变换的纠错编码数据块,并且基于约束选择一个; 并且发送所选择的数据块。 该方法可以包括向所接收的数据块添加对应于不同转换的枢轴数据。 在装置中,编码数据生成器被配置为基于接收到的数据块生成不同的编码数据块候选,并且选择器被配置为基于约束来选择候选之一作为编码数据输出。 编码数据生成器可以包括被配置为向接收的数据块应用一个或多个变换的变压器,以及被配置为对接收的数据块应用纠错的纠错码(ECC)编码器。 编码数据发生器和选择器可以包括在发射机中。

    Decoding methods and apparatus for fractional multidimensional trellis coded modulation systems
    10.
    发明授权
    Decoding methods and apparatus for fractional multidimensional trellis coded modulation systems 有权
    用于分数多维网格编码调制系统的解码方法和装置

    公开(公告)号:US08407570B1

    公开(公告)日:2013-03-26

    申请号:US13463401

    申请日:2012-05-03

    IPC分类号: H03M13/03

    摘要: Systems and methods for encoding user information and decoding signal vectors using fractional encoding/decoding and set partitioning. A fractional encoder can select a coset for transmitting or storing user information based on one or more deterministic bits and on encoded user information. The deterministic bits limit the encoder to using only a subset of the available signal vectors in a modulation scheme. A fractional decoder can receive a signal vector, and can find at least two nearest neighbors in each dimension. The fractional decoder can form a set of potential signal vectors using only the at least two nearest neighbors. The decoder may determine which of these potential signal vectors are valid within the fractional signaling scheme, and can decode the received signal vector based on the valid potential signal vectors.

    摘要翻译: 用于编码用户信息的系统和方法,并使用分数编码/解码和设置分区对信号向量进行解码。 分数编码器可以基于一个或多个确定性位和编码的用户信息来选择用于发送或存储用户信息的陪集。 确定性位将编码器限制为在调制方案中仅使用可用信号向量的子集。 分数解码器可以接收信号向量,并且可以在每个维度中找到至少两个最近的邻居。 分数解码器可以仅使用至少两个最近的邻居形成一组潜在的信号向量。 解码器可以在分数信令方案中确定这些潜在信号向量中哪一个是有效的,并且可以基于有效的电位信号向量对接收的信号向量进行解码。