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    High speed linear differential amplifier
    1.
    发明授权
    High speed linear differential amplifier 有权
    高速线性差分放大器

    公开(公告)号：US08189403B2

    公开(公告)日：2012-05-29

    申请号：US12817760

    申请日：2010-06-17

    申请人： Young-Soo Sohn ,  Jeong-Don Lim ,  Kwang-Il Park

    发明人： Young-Soo Sohn ,  Jeong-Don Lim ,  Kwang-Il Park

    IPC分类号： G11C7/00 ,  H03L7/00

    CPC分类号： H03F3/45183 ,  H03F1/3211 ,  H03F3/45179 ,  H03F3/45654 ,  H03F2200/453 ,  H03F2200/78 ,  H03F2203/45382 ,  H03F2203/45384 ,  H03F2203/45454 ,  H03F2203/45466 ,  H03F2203/45702

    摘要： A high speed linear differential amplifier (HSLDA) having automatic gain adjustment to maximize linearity regardless of manufacturing process, changes in temperature, or swing width change of the input signal. The HSLDA comprises a differential amplifier, and a control signal generator including a replica differential amplifier, a reference voltage generator, and a comparator. The comparator outputs a control signal that automatically adjusts the gain of the high speed linear differential amplifier and of the replica differential amplifier. The replica differential amplifier receives predetermined complementary voltages as input signals and outputs a replica output signal to the comparator. The reference voltage generator outputs a voltage to the comparator at which linearity of the output signal of the differential amplifier is maximized. The control signal equalizes the voltage level of the replica output signal and the reference voltage, and controls the gain of the differential amplifier.

    摘要翻译： 具有自动增益调整的高速线性差分放大器（HSLDA），以便与输入信号的制造过程，温度变化或摆幅宽度变化无关地最大化线性度。 HSLDA包括差分放大器和包括复制差分放大器，参考电压发生器和比较器的控制信号发生器。 比较器输出一个自动调节高速线性差分放大器和复制差分放大器增益的控制信号。 复制差分放大器接收预定的互补电压作为输入信号，并将复制输出信号输出到比较器。 参考电压发生器向差分放大器的输出信号的线性度最大化的比较器输出电压。 控制信号使复制输出信号的电压电平与参考电压相等，并控制差分放大器的增益。

    HIGH SPEED LINEAR DIFFERENTIAL AMPLIFIER
    2.
    发明申请
    HIGH SPEED LINEAR DIFFERENTIAL AMPLIFIER 有权
    高速线性差分放大器

    公开(公告)号：US20110001562A1

    公开(公告)日：2011-01-06

    申请号：US12817760

    申请日：2010-06-17

    申请人： Young-Soo Sohn ,  Jeong-Don Lim ,  Kwang-Il Park

    发明人： Young-Soo Sohn ,  Jeong-Don Lim ,  Kwang-Il Park

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45183 ,  H03F1/3211 ,  H03F3/45179 ,  H03F3/45654 ,  H03F2200/453 ,  H03F2200/78 ,  H03F2203/45382 ,  H03F2203/45384 ,  H03F2203/45454 ,  H03F2203/45466 ,  H03F2203/45702

    摘要： A high speed linear differential amplifier (HSLDA) having automatic gain adjustment to maximize linearity regardless of manufacturing process, changes in temperature, or swing width change of the input signal. The HSLDA comprises a differential amplifier, and a control signal generator including a replica differential amplifier, a reference voltage generator, and a comparator. The comparator outputs a control signal that automatically adjusts the gain of the high speed linear differential amplifier and of the replica differential amplifier. The replica differential amplifier receives predetermined complementary voltages as input signals and outputs a replica output signal to the comparator. The reference voltage generator outputs a voltage to the comparator at which linearity of the output signal of the differential amplifier is maximized. The control signal equalizes the voltage level of the replica output signal and the reference voltage, and controls the gain of the differential amplifier.

    摘要翻译： 具有自动增益调整的高速线性差分放大器（HSLDA），以便与输入信号的制造过程，温度变化或摆幅宽度变化无关地最大化线性度。 HSLDA包括差分放大器和包括复制差分放大器，参考电压发生器和比较器的控制信号发生器。 比较器输出一个自动调节高速线性差分放大器和复制差分放大器增益的控制信号。 复制差分放大器接收预定的互补电压作为输入信号，并将复制输出信号输出到比较器。 参考电压发生器向差分放大器的输出信号的线性度最大化的比较器输出电压。 控制信号使复制输出信号的电压电平与参考电压相等，并控制差分放大器的增益。

    SEMICONDUCTOR MEMORY DEVICE HAVING A LATENCY CONTROLLER
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING A LATENCY CONTROLLER 有权
    具有时间控制器的半导体存储器件

    公开(公告)号：US20100329049A1

    公开(公告)日：2010-12-30

    申请号：US12820364

    申请日：2010-06-22

    申请人： YOUNG-SOO SOHN ,  Jeong-Don Lim ,  Kwang-Il Park

    发明人： YOUNG-SOO SOHN ,  Jeong-Don Lim ,  Kwang-Il Park

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/109 ,  G11C7/222 ,  G11C2207/2272

    摘要： A semiconductor memory device includes a latency controller which provides a power-saving effect. The latency controller includes a first-in first-out (FIFO) register. After a read command is applied, when a precharge command or power-down command is applied, the latency controller outputs a latency signal corresponding to the applied read command and blocks application of sampling and transmission clock signals to the FIFO register.

    摘要翻译： 半导体存储器件包括提供省电效果的等待时间控制器。 等待时间控制器包括先进先出（FIFO）寄存器。 在应用读命令之后，当应用预充电命令或掉电命令时，等待时间控制器输出与所应用的读命令对应的等待时间信号，并阻止采样和发送时钟信号的应用到FIFO寄存器。

    Semiconductor memory device having a latency controller
    4.
    发明授权
    Semiconductor memory device having a latency controller 有权
    具有等待时间控制器的半导体存储器件

    公开(公告)号：US08254184B2

    公开(公告)日：2012-08-28

    申请号：US12820364

    申请日：2010-06-22

    申请人： Young-Soo Sohn ,  Jeong-Don Lim ,  Kwang-Il Park

    发明人： Young-Soo Sohn ,  Jeong-Don Lim ,  Kwang-Il Park

    IPC分类号： G11C7/00 ,  G11C5/14 ,  G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/109 ,  G11C7/222 ,  G11C2207/2272

    摘要： A semiconductor memory device includes a latency controller which provides a power-saving effect. The latency controller includes a first-in first-out (FIFO) register. After a read command is applied, when a precharge command or power-down command is applied, the latency controller outputs a latency signal corresponding to the applied read command and blocks application of sampling and transmission clock signals to the FIFO register.

    摘要翻译： 半导体存储器件包括提供省电效果的等待时间控制器。 等待时间控制器包括先进先出（FIFO）寄存器。 在应用读命令之后，当应用预充电命令或掉电命令时，等待时间控制器输出与所应用的读命令对应的等待时间信号，并阻止采样和发送时钟信号的应用到FIFO寄存器。

    Majority voter circuits and semiconductor devices including the same
    5.
    发明授权
    Majority voter circuits and semiconductor devices including the same 有权
    多数选民电路和半导体器件包括相同

    公开(公告)号：US07688102B2

    公开(公告)日：2010-03-30

    申请号：US11819600

    申请日：2007-06-28

    申请人： Seung-Jun Bae ,  Jeong-Don Lim ,  Gil-Shin Moon ,  Kwang-Il Park

    发明人： Seung-Jun Bae ,  Jeong-Don Lim ,  Gil-Shin Moon ,  Kwang-Il Park

    IPC分类号： H03K19/003

    CPC分类号： H03K19/23

    摘要： A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.

    摘要翻译： 多数选民电路被配置为基于第一输入数据和反相的第一输入数据生成选择信号。 第一输入数据和反相的第一输入数据都包括奇数位，奇数位包括第一类型的位和第二类型的位。 所生成的选择信号表示第一输入数据中的第一类型和第二类型的比特大多数。

    CIRCUIT AND METHOD FOR SAMPLING VALID COMMAND USING EXTENDED VALID ADDRESS WINDOW IN DOUBLE PUMPED ADDRESS SCHEME MEMORY DEVICE
    6.
    发明申请
    CIRCUIT AND METHOD FOR SAMPLING VALID COMMAND USING EXTENDED VALID ADDRESS WINDOW IN DOUBLE PUMPED ADDRESS SCHEME MEMORY DEVICE 审中-公开
    在双重抽取地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法

    公开(公告)号：US20100091600A1

    公开(公告)日：2010-04-15

    申请号：US12635785

    申请日：2009-12-11

    申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

    发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

    IPC分类号： G11C8/00 ,  G11C8/18

    CPC分类号： G06F12/02 ,  G11C7/1078 ,  G11C7/109

    摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.

    摘要翻译： 提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。 扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

    Majority voter circuits and semiconductor devices including the same
    7.
    发明申请
    Majority voter circuits and semiconductor devices including the same 有权
    多数选民电路和半导体器件包括相同

    公开(公告)号：US20080001626A1

    公开(公告)日：2008-01-03

    申请号：US11819600

    申请日：2007-06-28

    申请人： Seung-Jun Bae ,  Jeong-Don Lim ,  Gil-Shin Moon ,  Kwang-Il Park

    发明人： Seung-Jun Bae ,  Jeong-Don Lim ,  Gil-Shin Moon ,  Kwang-Il Park

    IPC分类号： H03K19/23

    CPC分类号： H03K19/23

    摘要： A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.

    摘要翻译： 多数选民电路被配置为基于第一输入数据和反相的第一输入数据生成选择信号。 第一输入数据和反相的第一输入数据都包括奇数位，奇数位包括第一类型的位和第二类型的位。 所生成的选择信号表示第一输入数据中的第一类型和第二类型的比特大多数。

    Semiconductor memory device and method of controlling the same
    8.
    发明授权
    Semiconductor memory device and method of controlling the same 有权
    半导体存储器件及其控制方法

    公开(公告)号：US08649238B2

    公开(公告)日：2014-02-11

    申请号：US13078218

    申请日：2011-04-01

    申请人： Dong-Min Kim ,  Young-Soo Sohn ,  Seung-Jun Bae ,  Kwang-Il Park

    发明人： Dong-Min Kim ,  Young-Soo Sohn ,  Seung-Jun Bae ,  Kwang-Il Park

    IPC分类号： G11C8/00

    CPC分类号： G11C8/12 ,  G11C8/18

    摘要： A semiconductor memory device includes a memory cell array, an address control unit and a logic circuit. The memory cell array includes a plurality of banks which are divided into a first bank block and a second bank block. The address control unit accesses the memory cell array. The logic circuit controls the address control unit based on a command and an address signal such that the first and second bank blocks commonly operate in a first operation mode, and the first and second bank blocks individually operate in a second operation mode.

    摘要翻译： 半导体存储器件包括存储单元阵列，地址控制单元和逻辑电路。 存储单元阵列包括被划分成第一存储块和第二存储块的多个存储体。 地址控制单元访问存储单元阵列。 逻辑电路基于命令和地址信号控制地址控制单元，使得第一和第二存储体块以第一操作模式共同操作，并且第一和第二存储体块以第二操作模式分别操作。

    Data write training method
    9.
    发明授权
    Data write training method 有权
    数据写入训练方法

    公开(公告)号：US08593901B2

    公开(公告)日：2013-11-26

    申请号：US13868425

    申请日：2013-04-23

    申请人： Tae-Young Oh ,  Young-Soo Sohn ,  Seung-Jun Bae ,  Kwang-Il Park

    发明人： Tae-Young Oh ,  Young-Soo Sohn ,  Seung-Jun Bae ,  Kwang-Il Park

    IPC分类号： G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/1087 ,  G11C7/1093 ,  G11C2207/2254

    摘要： Embodiments may be directed to a method of operating a semiconductor device, the method including receiving a first write training command, receiving a first write data responsive to the first write training command through a first data line, and transmitting the first write data through a second data line. Transmitting the first write data is performed without an additional training command.

    摘要翻译： 实施例可以涉及一种操作半导体器件的方法，所述方法包括接收第一写入训练命令，响应于通过第一数据线的第一写入训练命令接收第一写入数据，以及通过第二数据线发送第一写入数据 数据线。 在不附加训练命令的情况下执行发送第一写入数据。