公开(公告)号：US07050316B1

公开(公告)日：2006-05-23

申请号：US10797207

申请日：2004-03-09

申请人： Ya-Fen Lin ,  Elbert Lin ,  Dana Lee ,  Bomy Chen ,  Hung Q. Nguyen

发明人： Ya-Fen Lin ,  Elbert Lin ,  Dana Lee ,  Bomy Chen ,  Hung Q. Nguyen

IPC分类号： G11C15/00

CPC分类号： G11C15/046 ,  G11C13/0004

摘要： A differential sensing content addressable memory cell without any word lines connected to the cells in the same row comprises a first bit line for supplying a first bit. A first storage element has a first phase change resistor for storing a first stored bit, which is connected in series with a first diode. The first storage element is connected to the first bit line. A second bit line supplies a second bit, with the second bit being an inverse of the first bit. A second storage element has a second phase change resistor for storing a second stored bit, which is connected in series with a second diode. The second storage element is connected to the second bit line. A match line is connected to the first and second storage elements for indicating whether a match occurred between the first bit and the first stored bit, and between the second bit and the second stored bit

摘要翻译： 差分感测内容可寻址存储单元，没有连接到同一行中的单元的任何字线包括用于提供第一位的第一位线。 第一存储元件具有第一相变电阻器，用于存储与第一二极管串联连接的第一存储位。 第一存储元件连接到第一位线。 第二位线提供第二位，第二位是第一位的倒数。 第二存储元件具有用于存储与第二二极管串联连接的第二存储位的第二相变电阻器。 第二存储元件连接到第二位线。 匹配线连接到第一和第二存储元件，用于指示在第一位和第一存储位之间以及第二位和第二存储位之间是否发生匹配

公开(公告)号：US07403418B2

公开(公告)日：2008-07-22

申请号：US11241582

申请日：2005-09-30

申请人： Ya-Fen Lin ,  Elbert Lin ,  Hieu Van Tran ,  Jack Edward Frayer ,  Bomy Chen

发明人： Ya-Fen Lin ,  Elbert Lin ,  Hieu Van Tran ,  Jack Edward Frayer ,  Bomy Chen

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C16/08

摘要： A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.

公开(公告)号：US20070076489A1

公开(公告)日：2007-04-05

申请号：US11241582

申请日：2005-09-30

申请人： Ya-Fen Lin ,  Elbert Lin ,  Hieu Tran ,  Jack Frayer ,  Bomy Chen

发明人： Ya-Fen Lin ,  Elbert Lin ,  Hieu Tran ,  Jack Frayer ,  Bomy Chen

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C16/08

摘要： A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.

公开(公告)号：US06853584B2

公开(公告)日：2005-02-08

申请号：US10428742

申请日：2003-05-02

申请人： Hung Q. Nguyen ,  Sang Thanh Nguyen ,  Elbert Lin ,  Anh Ly

发明人： Hung Q. Nguyen ,  Sang Thanh Nguyen ,  Elbert Lin ,  Anh Ly

IPC分类号： G11C5/14 ,  G11C11/34 ,  G11C16/06 ,  G11C16/30

CPC分类号： G11C16/30 ,  G11C5/147

摘要： A non-volatile memory semiconductor device has a circuit to compensate for the variation in the data pattern to be programmed. The variation in the data patter creates a variation in the current requirement. The array receives a plurality of data pattern signals which affect the total amount of current flowing into a plurality of columns and into the memory array. A high voltage source generates an output which is supplied along a conducting path connected to the group of columns. A pass transistor is in the conducting path controlling the current flow in the conducting path. A current source has a first terminal and a second terminal with the first terminal connected to the output of the high voltage generator and the second terminal connected to the gate of the pass transistor. A plurality of current sources are collectively connected to a node. Each of the plurality of current sources receives a plurality of second signals with each second signal being an inverse of the first signal, and controlling the total amount of current flowing through the node. A current mirror circuit is connected to the node and to the gate of the pass transistor and controls the pass transistor in response to the amount of current flowing through the node.

摘要翻译： 非易失性存储器半导体器件具有用于补偿要编程的数据模式的变化的电路。 数据模式的变化会导致当前需求的变化。 阵列接收多个数据模式信号，这些数据模式信号影响流入多个列的电流的总量并进入存储器阵列。 高电压源产生沿着连接到一组列的导电路径提供的输出。 传导晶体管处于控制导电路径中的电流的导电路径中。 电流源具有第一端子和第二端子，其第一端子连接到高电压发生器的输出端，第二端子连接到传输晶体管的栅极。 多个电流源共同连接到节点。 多个电流源中的每一个接收多个第二信号，其中每个第二信号是第一信号的倒数，并且控制流过节点的总电流量。 电流镜电路连接到节点和传输晶体管的栅极，并根据流过节点的电流量来控制传输晶体管。