公开(公告)号：US20080013374A1

公开(公告)日：2008-01-17

申请号：US11862157

申请日：2007-09-26

申请人： Yan Li ,  Long Pham

发明人： Yan Li ,  Long Pham

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a lower page of data to have a voltage threshold (VTH) that falls within a first VTH distribution or a higher, intermediate VTH distribution. Subsequently, the non-volatile storage elements with the first VTH distribution either remain there, or are programmed to a second VTH distribution, based on an upper page of data. The non-volatile storage elements with the intermediate VTH distribution are programmed to third and fourth VTH distributions. The non-volatile storage elements being programmed to the third VTH distribution are specially identified and tracked. Verification of the non-volatile storage elements being programmed to the fourth VTH distribution is initiated after one of the identified non-volatile storage elements transitions to the third VTH distribution from the intermediate VTH distribution.

摘要翻译： 在非易失性存储器中，自适应地设定程序验证的启动，从而减少编程时间。 在一种方法中，非易失性存储元件基于较低数据页被编程以具有落在第一V TH分布内的电压阈值（V TH TH TH），或 较高的中间V TH分配。 随后，具有第一V TH分布的非易失性存储元件基于数据的上部页面保留在那里，或被编程到第二V TH分配。 具有中间V TH分布的非易失性存储元件被编程到第三和第四V分布。 专门识别和跟踪正在编程到第三VTH分配的非易失性存储元件。 正在编程到第四VTH分布的非易失性存储元件的验证在所识别的非易失性存储元件中的一个转移到第三V TH分布之后启动， 中间V TH分配。

公开(公告)号：US20070097747A1

公开(公告)日：2007-05-03

申请号：US11259799

申请日：2005-10-27

申请人： Yan Li ,  Long Pham

发明人： Yan Li ,  Long Pham

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a lower page of data to have a voltage threshold (VTH) that falls within a first VTH distribution or a higher, intermediate VTH distribution. Subsequently, the non-volatile storage elements with the first VTH distribution either remain there, or are programmed to a second VTH distribution, based on an upper page of data. The non-volatile storage elements with the intermediate VTH distribution are programmed to third and fourth VTH distributions. The non-volatile storage elements being programmed to the third VTH distribution are specially identified and tracked. Verification of the non-volatile storage elements being programmed to the fourth VTH distribution is initiated after one of the identified non-volatile storage elements transitions to the third VTH distribution from the intermediate VTH distribution.

摘要翻译： 在非易失性存储器中，自适应地设定程序验证的启动，从而减少编程时间。 在一种方法中，非易失性存储元件基于较低数据页被编程以具有落在第一V TH分布内的电压阈值（V TH TH TH），或 较高的中间V TH分配。 随后，具有第一V TH分布的非易失性存储元件基于数据的上部页面保留在那里，或被编程到第二V TH分配。 具有中间V TH分布的非易失性存储元件被编程到第三和第四V分布。 专门识别和跟踪正在编程到第三VTH分配的非易失性存储元件。 正在编程到第四VTH分布的非易失性存储元件的验证在所识别的非易失性存储元件中的一个转移到第三V TH分布之后启动， 中间V TH分配。

公开(公告)号：US07366022B2

公开(公告)日：2008-04-29

申请号：US11259799

申请日：2005-10-27

申请人： Yan Li ,  Long Pham

发明人： Yan Li ,  Long Pham

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a lower page of data to have a voltage threshold (VTH) that falls within a first VTH distribution or a higher, intermediate VTH distribution. Subsequently, the non-volatile storage elements with the first VTH distribution either remain there, or are programmed to a second VTH distribution, based on an upper page of data. The non-volatile storage elements with the intermediate VTH distribution are programmed to third and fourth VTH distributions. The non-volatile storage elements being programmed to the third VTH distribution are specially identified and tracked. Verification of the non-volatile storage elements being programmed to the fourth VTH distribution is initiated after one of the identified non-volatile storage elements transitions to the third VTH distribution from the intermediate VTH distribution.

摘要翻译： 在非易失性存储器中，自适应地设定程序验证的启动，从而减少编程时间。 在一种方法中，非易失性存储元件基于较低数据页被编程以具有落在第一V TH分布内的电压阈值（V TH TH TH），或 较高的中间V TH分配。 随后，具有第一V TH分布的非易失性存储元件基于数据的上部页面保留在那里，或被编程到第二V TH分配。 具有中间V TH分布的非易失性存储元件被编程到第三和第四V分布。 专门识别和跟踪正在编程到第三VTH分配的非易失性存储元件。 正在编程到第四VTH分布的非易失性存储元件的验证在所识别的非易失性存储元件中的一个转移到第三V TH分布之后启动， 中间V TH分配。

公开(公告)号：US20070097749A1

公开(公告)日：2007-05-03

申请号：US11260658

申请日：2005-10-27

申请人： Yan Li ,  Long Pham

发明人： Yan Li ,  Long Pham

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a lower page of data to have a voltage threshold (VTH) that falls within a first VTH distribution or a higher, intermediate VTH distribution. Subsequently, the non-volatile storage elements with the first VTH distribution either remain there, or are programmed to a second VTH distribution, based on an upper page of data. The non-volatile storage elements with the intermediate VTH distribution are programmed to third and fourth VTH distributions. The non-volatile storage elements being programmed to the third VTH distribution are specially identified and tracked. Verification of the non-volatile storage elements being programmed to the fourth VTH distribution is initiated after one of the identified non-volatile storage elements transitions to the third VTH distribution from the intermediate VTH distribution.

公开(公告)号：US07492634B2

公开(公告)日：2009-02-17

申请号：US11862157

申请日：2007-09-26

申请人： Yan Li ,  Long Pham

发明人： Yan Li ,  Long Pham

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a lower page of data to have a voltage threshold (VTH) that falls within a first VTH distribution or a higher, intermediate VTH distribution. Subsequently, the non-volatile storage elements with the first VTH distribution either remain there, or are programmed to a second VTH distribution, based on an upper page of data. The non-volatile storage elements with the intermediate VTH distribution are programmed to third and fourth VTH distributions. The non-volatile storage elements being programmed to the third VTH distribution are specially identified and tracked. Verification of the non-volatile storage elements being programmed to the fourth VTH distribution is initiated after one of the identified non-volatile storage elements transitions to the third VTH distribution from the intermediate VTH distribution.

摘要翻译： 在非易失性存储器中，自适应地设定程序验证的启动，从而减少编程时间。 在一种方法中，非易失性存储元件基于较低数据页被编程以具有落在第一VTH分布或更高的中间VTH分布内的电压阈值（VTH）。 随后，具有第一VTH分配的非易失性存储元件基于数据的上部页面保留在那里，或被编程到第二VTH分发。 具有中间VTH分布的非易失性存储元件被编程为第三和第四VTH分布。 被编程到第三VTH分配的非易失性存储元件被特别地识别和跟踪。 被编程到第四VTH分布的非易失性存储元件的验证在所识别的非易失性存储元件中的一个从中间VTH分布转换到第三VTH分布之后启动。

公开(公告)号：US07301817B2

公开(公告)日：2007-11-27

申请号：US11260658

申请日：2005-10-27

申请人： Yan Li ,  Long Pham

发明人： Yan Li ,  Long Pham

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a lower page of data to have a voltage threshold (VTH) that falls within a first VTH distribution or a higher, intermediate VTH distribution. Subsequently, the non-volatile storage elements with the first VTH distribution either remain there, or are programmed to a second VTH distribution, based on an upper page of data. The non-volatile storage elements with the intermediate VTH distribution are programmed to third and fourth VTH distributions. The non-volatile storage elements being programmed to the third VTH distribution are specially identified and tracked. Verification of the non-volatile storage elements being programmed to the fourth VTH distribution is initiated after one of the identified non-volatile storage elements transitions to the third VTH distribution from the intermediate VTH distribution.

摘要翻译： 在非易失性存储器中，自适应地设定程序验证的启动，从而减少编程时间。 在一种方法中，非易失性存储元件基于较低数据页被编程以具有落在第一V TH分布内的电压阈值（V TH TH TH），或 较高的中间V TH分配。 随后，具有第一V TH分布的非易失性存储元件基于数据的上部页面保留在那里，或被编程到第二V TH分配。 具有中间V TH分布的非易失性存储元件被编程到第三和第四V分布。 专门识别和跟踪正在编程到第三VTH分配的非易失性存储元件。 正在编程到第四VTH分布的非易失性存储元件的验证在所识别的非易失性存储元件中的一个转移到第三V TH分布之后启动， 中间V TH分配。

公开(公告)号：US07715255B2

公开(公告)日：2010-05-11

申请号：US11763287

申请日：2007-06-14

申请人： Loc Tu ,  Jian Chen ,  Alex Mak ,  Tien-Chien Kuo ,  Long Pham

发明人： Loc Tu ,  Jian Chen ,  Alex Mak ,  Tien-Chien Kuo ,  Long Pham

IPC分类号： G11C7/00

CPC分类号： H01L22/20 ,  H01L27/108 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11524

摘要： Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be readdressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

摘要翻译： 存储器管芯具有可编程芯片使能电路，以允许在封装和/或可编程芯片地址电路之后禁止特定存储器管芯，以允许特定存储器管芯在封装之后被读取。 在多芯片存储器封装中，可以通过可覆盖从控制器或主机设备接收的主芯片使能信号的可编程电路来禁止与存储器封装隔离的封装级测试失败的存储器管芯。 为了提供连续的地址范围，可以使用另一个可替代由焊盘键合提供的唯一芯片地址的可编程电路来读取一个或多个无缺陷存储器管芯。 封装后的存储器芯片也可以被独立于检测出错的存储器芯片而被读取。

公开(公告)号：US07477545B2

公开(公告)日：2009-01-13

申请号：US11763292

申请日：2007-06-14

申请人： Loc Tu ,  Jian Chen ,  Alex Mak ,  Tien-Chien Kuo ,  Long Pham

发明人： Loc Tu ,  Jian Chen ,  Alex Mak ,  Tien-Chien Kuo ,  Long Pham

IPC分类号： G11C16/04

CPC分类号： G11C29/88 ,  G11C5/04

摘要： Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

摘要翻译： 存储器管芯具有可编程芯片使能电路，以允许在封装和/或可编程芯片地址电路之后禁止特定存储器管芯，以允许特定存储器管芯在封装之后被读取。 在多芯片存储器封装中，可以通过可覆盖从控制器或主机设备接收的主芯片使能信号的可编程电路来禁止与存储器封装隔离的封装级测试失败的存储器管芯。 为了提供连续的地址范围，可以使用替代由焊盘键合提供的唯一芯片地址的另一个可编程电路来重新寻址无缺陷存储器管芯中的一个或多个。 封装后的存储器芯片也可以被独立于检测出错的存储器芯片而被读取。

公开(公告)号：US20050117401A1

公开(公告)日：2005-06-02

申请号：US11028906

申请日：2005-01-03

申请人： Jian Chen ,  Long Pham ,  Alexander Mak

发明人： Jian Chen ,  Long Pham ,  Alexander Mak

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/34 ,  G11C29/42 ,  G11C5/00

CPC分类号： G11C16/3431 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/3418

摘要： Techniques of overcoming a degradation of the apparent charge levels stored in one row of memory cells as a result of subsequently programming an adjacent row of memory cells. After storing the data of the subsequently programmed row elsewhere, the charge levels of its cells are driven to common level. The charge levels of the first row of cells then have a uniform influence from the charge levels of the second row, and, as a result, the chance of successfully reading the data stored in the first row is significantly increased.

公开(公告)号：US20080311684A1

公开(公告)日：2008-12-18

申请号：US11763287

申请日：2007-06-14

申请人： Loc Tu ,  Jian Chen ,  Alex Mak ,  Tien-chien Kuo ,  Long Pham

发明人： Loc Tu ,  Jian Chen ,  Alex Mak ,  Tien-chien Kuo ,  Long Pham

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  H01L27/108 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11524

摘要： Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

摘要翻译： 存储器管芯具有可编程芯片使能电路，以允许在封装和/或可编程芯片地址电路之后禁止特定存储器管芯，以允许特定存储器管芯在封装之后被读取。 在多芯片存储器封装中，可以通过可覆盖从控制器或主机设备接收的主芯片使能信号的可编程电路来禁止与存储器封装隔离的封装级测试失败的存储器管芯。 为了提供连续的地址范围，可以使用替代由焊盘键合提供的唯一芯片地址的另一个可编程电路来重新寻址无缺陷存储器管芯中的一个或多个。 封装后的存储器芯片也可以被独立于检测出错的存储器芯片而被读取。