公开(公告)号：US20110222345A1

公开(公告)日：2011-09-15

申请号：US13114481

申请日：2011-05-24

申请人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

发明人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C2211/5621

摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

摘要翻译： 能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有降低读取和编程/验证操作期间的功耗的特征。 读取或编程验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。 在一个方面，当被确定为处于与当前感测周期无关的状态时，被并联感测的组中的选择性存储单元的导通电流关闭。 另一方面，通过预先启动延长周期的任何操作来最小化功耗周期。 在程序/验证操作中，不编程的单元在程序阶段中将其位线充电。 当一组这些位线避免在每个程序阶段的过程中重新充电时，节省电力。

公开(公告)号：US20120243332A1

公开(公告)日：2012-09-27

申请号：US13430155

申请日：2012-03-26

申请人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

发明人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

IPC分类号： G11C16/10

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C2211/5621

摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

摘要翻译： 能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有降低读取和编程/验证操作期间的功耗的特征。 读取或编程验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。 在一个方面，当被确定为处于与当前感测周期无关的状态时，被并联感测的组中的选择性存储单元的导通电流关闭。 另一方面，通过预先启动延长周期的任何操作来最小化功耗周期。 在程序/验证操作中，不编程的单元在程序阶段中将其位线充电。 当一组这些位线避免在每个程序阶段的过程中重新充电时，节省电力。

公开(公告)号：US08154923B2

公开(公告)日：2012-04-10

申请号：US13114481

申请日：2011-05-24

申请人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

发明人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C2211/5621

摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

摘要翻译： 能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有降低读取和编程/验证操作期间的功耗的特征。 读取或编程验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。 在一个方面，当被确定为处于与当前感测周期无关的状态时，被并联感测的组中的选择性存储单元的导通电流关闭。 另一方面，通过预先启动延长周期的任何操作来最小化功耗周期。 在程序/验证操作中，不编程的单元在程序阶段中将其位线充电。 当一组这些位线避免在每个程序阶段的过程中重新充电时，节省电力。

公开(公告)号：US07570513B2

公开(公告)日：2009-08-04

申请号：US11534307

申请日：2006-09-22

申请人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

发明人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C2211/5621

摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

摘要翻译： 能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有降低读取和编程/验证操作期间的功耗的特征。 读取或编程验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。 在一个方面，当被确定为处于与当前感测周期无关的状态时，被并联感测的组中的选择性存储单元的导通电流关闭。 另一方面，通过预先启动延长周期的任何操作来最小化功耗周期。 在程序/验证操作中，不编程的单元在程序阶段中将其位线充电。 当一组这些位线避免在每个程序阶段的过程中重新充电时，节省电力。

公开(公告)号：US08542529B2

公开(公告)日：2013-09-24

申请号：US13430155

申请日：2012-03-26

申请人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

发明人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C2211/5621

摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

公开(公告)号：US07957185B2

公开(公告)日：2011-06-07

申请号：US11534297

申请日：2006-09-22

申请人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

发明人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C2211/5621

摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

摘要翻译： 能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有降低读取和编程/验证操作期间的功耗的特征。 读取或编程验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。 在一个方面，当被确定为处于与当前感测周期无关的状态时，被并联感测的组中的选择性存储单元的导通电流关闭。 另一方面，通过预先启动延长周期的任何操作来最小化功耗周期。 在程序/验证操作中，不编程的单元在程序阶段中将其位线充电。 当一组这些位线避免在每个程序阶段的过程中重新充电时，节省电力。

公开(公告)号：US07251160B2

公开(公告)日：2007-07-31

申请号：US11083514

申请日：2005-03-16

申请人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

发明人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C2211/5621

摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

摘要翻译： 能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有降低读取和编程/验证操作期间的功耗的特征。 读取或编程验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。 在一个方面，当被确定为处于与当前感测周期无关的状态时，被并联感测的组中的选择性存储单元的导通电流关闭。 另一方面，通过预先启动延长周期的任何操作来最小化功耗周期。 在程序/验证操作中，不编程的单元在程序阶段中将其位线充电。 当一组这些位线避免在每个程序阶段的过程中重新充电时，节省电力。

公开(公告)号：US20060209592A1

公开(公告)日：2006-09-21

申请号：US11083514

申请日：2005-03-16

申请人： Yan Li ,  Seungpil Lee ,  Siu Chan

发明人： Yan Li ,  Seungpil Lee ,  Siu Chan

IPC分类号： G11C16/04

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C2211/5621

摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

公开(公告)号：US20130070530A1

公开(公告)日：2013-03-21

申请号：US13622045

申请日：2012-09-18

申请人： Jian Chen ,  Sergei Gorobets ,  Steven Sprouse ,  Tien-Chien Kuo ,  Yan Li ,  Seungpil Lee ,  Alex Mak ,  Deepanshu Dutta ,  Masaaki Higashitani

发明人： Jian Chen ,  Sergei Gorobets ,  Steven Sprouse ,  Tien-Chien Kuo ,  Yan Li ,  Seungpil Lee ,  Alex Mak ,  Deepanshu Dutta ,  Masaaki Higashitani

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C5/063 ,  G11C11/5628 ,  G11C2211/5641

摘要： A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.

摘要翻译： 公开了一种非易失性存储系统，其包括设计用于高耐久性和比其他非易失性存储器单元更低保持性的非易失性存储器单元。

公开(公告)号：US20070014161A1

公开(公告)日：2007-01-18

申请号：US11534297

申请日：2006-09-22

申请人： Yan Li ,  Seungpil Lee ,  Siu Chan

发明人： Yan Li ,  Seungpil Lee ,  Siu Chan

IPC分类号： G11C11/34 ,  G11C7/00 ,  G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C2211/5621

摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

摘要翻译： 能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有降低读取和编程/验证操作期间的功耗的特征。 读取或编程验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。 在一个方面，当被确定为处于与当前感测周期无关的状态时，被并联感测的组中的选择性存储单元的导通电流关闭。 另一方面，通过预先启动延长周期的任何操作来最小化功耗周期。 在程序/验证操作中，不编程的单元在程序阶段中将其位线充电。 当一组这些位线避免在每个程序阶段的过程中重新充电时，节省电力。