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公开(公告)号：US20240215237A1
公开(公告)日：2024-06-27
申请号：US18090049
申请日：2022-12-28
发明人： Yi YANG , Tingting GAO , Xiaoxin LIU , Wei YUAN , Xiaolong DU , Changzhi SUN , Zhihao SONG , Shan LI , Zhiliang XIA , Zongliang HUO
摘要： A method for fabricating a 3D memory device includes forming a sacrificial layer over a substrate, forming a first dielectric stack over the sacrificial layer, forming a channel hole structure, forming an opening that exposes the sacrificial layer, removing the sacrificial layer to create a cavity and expose a part of the channel hole structure, forming a semiconductor layer to fill the cavity, filling the opening with a filling structure, and forming a second dielectric stack over the filling structure. The opening is made for a gate line slit (GLS) structure.
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公开(公告)号：US20220406813A1
公开(公告)日：2022-12-22
申请号：US17845308
申请日：2022-06-21
发明人： Tingting GAO , Zhiliang XIA , Xiaoxin LIU , Changzhi SUN , Xiaolong DU
IPC分类号： H01L27/11582 , H01L27/11556
摘要： The present application provides a three-dimensional memory and a fabrication method for the same. The method includes forming a storage stack structure on a substrate and forming a storage channel structure that penetrates the storage stack structure, forming a selection stack structure stacked on the storage stack structure and forming a selection channel structure that penetrates the selection stack structure and is connected to the storage channel structure. The width of the selection channel structure is smaller than the width of the storage channel structure on a plane parallel to the substrate and forming a TSG cut structure that penetrates the selection stack structure. The three-dimensional memory and the fabrication method for the same increases the process window for the TSG cut structure formed between the selection channel structures and improves the storage density.
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3.发明公开公开(公告)号：US20240179901A1
公开(公告)日：2024-05-30
申请号：US18082080
申请日：2022-12-15
发明人： Kun ZHANG , Wenxi ZHOU , Linchun WU , Yuhui HAN , Changzhi SUN , Zhiliang XIA , Zongliang HUO
IPC分类号： H10B43/20 , H01L21/28 , H01L29/423 , H01L29/792
CPC分类号： H10B43/20 , H01L29/40117 , H01L29/42348 , H01L29/7926
摘要： A 3D memory device includes a conductor/insulator stack containing a conductive layer and a dielectric layer alternatingly stacked, channel hole structures in a first region of memory cells in the conductor/insulator stack, a blocking structure adjacent to the first region, and a dummy channel hole structure in the first region. The dummy channel hole structure is adjacent to the blocking structure, and includes a dielectric material that fills a channel hole to form a first dielectric filling structure.
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公开(公告)号：US20240099008A1
公开(公告)日：2024-03-21
申请号：US17945703
申请日：2022-09-15
发明人： Tingting GAO , ZhiLiang XIA , Xiaoxin LIU , Xiaolong DU , Changzhi SUN , Jiayi LIU , ZongLiang HUO
IPC分类号： H01L27/1157 , H01L27/11582
CPC分类号： H01L27/1157 , H01L27/11582
摘要： According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack structure that includes alternating insulating layers and word line layers. The semiconductor device also includes a first channel structure extending through the stack structure, a first top select gate (TSG) layer over the stack structure, and a second TSG layer over the first TSG layer. The semiconductor device further includes a second channel structure extending through the first and second TSG layers, where the second channel structure is positioned over and coupled to the first channel structure.
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