公开(公告)号：US20220005828A1

公开(公告)日：2022-01-06

申请号：US17476206

申请日：2021-09-15

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Yuhui HAN

IPC分类号： H01L27/11582 ,  H01L27/1157

摘要： Aspects of the disclosure provide methods of manufacturing a semiconductor device. In a method, a stack of alternating gate layers and insulating layers is formed over a first region and a second region of a substrate of the semiconductor device. The stack of alternating gate layers and insulating layers is of a stair-step form over the second region of the substrate. A channel structure is formed over the first region and dummy channel structures are formed over the second region. The dummy channel structures includes a first dummy channel structure disposed through a first stair region of the stair-step form, a second dummy channel structure disposed through a second stair region of the stair-step form adjacent to the first stair region, and a third dummy channel structure disposed at a boundary between the first stair region and the second stair region.

公开(公告)号：US20240203908A1

公开(公告)日：2024-06-20

申请号：US18594895

申请日：2024-03-04

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Yuhui HAN ,  Zhiliang XIA ,  Wenxi ZHOU

IPC分类号： H01L23/00 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC分类号： H01L23/562 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

摘要： A semiconductor device includes a first stack of layers stacked on a substrate. The first stack of layers includes a source connection layer that is formed by replacing source sacrificial layers. The semiconductor device includes a channel structure that extends in the first stack of layers. The channel structure includes a channel layer that is in contact with the source connection layer in the first stack of layers. Further, the semiconductor device includes a shield structure formed in the first stack of layers. The shied structure encloses a stack of layers without the source connection layer.

公开(公告)号：US20240179901A1

公开(公告)日：2024-05-30

申请号：US18082080

申请日：2022-12-15

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Kun ZHANG ,  Wenxi ZHOU ,  Linchun WU ,  Yuhui HAN ,  Changzhi SUN ,  Zhiliang XIA ,  Zongliang HUO

IPC分类号： H10B43/20 ,  H01L21/28 ,  H01L29/423 ,  H01L29/792

CPC分类号： H10B43/20 ,  H01L29/40117 ,  H01L29/42348 ,  H01L29/7926

摘要： A 3D memory device includes a conductor/insulator stack containing a conductive layer and a dielectric layer alternatingly stacked, channel hole structures in a first region of memory cells in the conductor/insulator stack, a blocking structure adjacent to the first region, and a dummy channel hole structure in the first region. The dummy channel hole structure is adjacent to the blocking structure, and includes a dielectric material that fills a channel hole to form a first dielectric filling structure.

公开(公告)号：US20210233870A1

公开(公告)日：2021-07-29

申请号：US17113442

申请日：2020-12-07

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Yuhui HAN ,  Zhiliang XIA ,  Wenxi ZHOU

IPC分类号： H01L23/00 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

摘要： A semiconductor device includes a first stack of layers stacked on a substrate. The first stack of layers includes a source connection layer that is formed by replacing source sacrificial layers. The semiconductor device includes a channel structure that extends in the first stack of layers. The channel structure includes a channel layer that is in contact with the source connection layer in the first stack of layers. Further, the semiconductor device includes a shield structure formed in the first stack of layers. The shied structure encloses a stack of layers without the source connection layer.

公开(公告)号：US20210050368A1

公开(公告)日：2021-02-18

申请号：US16684812

申请日：2019-11-15

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Yuhui HAN

IPC分类号： H01L27/11582 ,  H01L27/1157

摘要： Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a substrate, a plurality of gate layers, and a plurality of insulating layers. The plurality of gate layers and the plurality of insulating layers are stacked alternately over a first region of the substrate and are stacked of a stair-step form over a second region of the substrate. The semiconductor device also includes a channel structure that is disposed over the first region and through the plurality of gate layers and the plurality of insulating layers. The channel structure and the plurality of gate layers form a stack of transistors in a series configuration with the plurality of gate layers being a plurality of gates for the stack of transistors. The semiconductor device also includes a first dummy channel structure that is disposed through a first stair region of the stair-step form, a second dummy channel structure that is disposed through a second stair region of the stair-step form adjacent to the first stair region, and a third dummy channel structure that is disposed at a boundary between the first stair region and the second stair region.