公开(公告)号：US4081752A

公开(公告)日：1978-03-28

申请号：US686214

申请日：1976-05-13

申请人： Yasuaki Sumi

发明人： Yasuaki Sumi

IPC分类号： H03J5/02 ,  H04B1/26 ,  H04B1/32

CPC分类号： H04B1/0092 ,  H03J5/0281 ,  H04B1/26

摘要： A scanning type frequency synthesized receiver utilizing a voltage controlled oscillator (VCO) for producing a local oscillator signal. The control voltage for the VCO is provided in response to the division rate of a programmable divider. A control circuit programs the divider which control circuit operates to vary the divisor of the divider within a predetermined range as determined by information stored in a memory corresponding to a range of frequencies in a frequency band to be scanned and received by the receiver. Upon a command signal the control circuit operates to vary the divisor of the divider either up or down to cause the frequency of VCO, and thereby the receiver, to scan in a given direction and upon a signal being received the variation of the divider divisor and the receiver scanning is terminated. The VCO can be scanned either up or down in frequency, and the scanning can be either from the upper (or lower) end of a frequency range back to the lower (or upper) end and then reversed or a repetitive scanning from one end of the range to the other in the same direction. In the preferred embodiment disclosed is a multiband scanning receiver in which the stored information for the control circuit corresponds to the extremities of each of a plurality of frequency bands, the information corresponding to a particular band being utilized in response to selection of the band for reception by a band switching means.

摘要翻译： 利用压控振荡器（VCO）产生本地振荡器信号的扫描型频率合成接收机。 响应于可编程分频器的分频率来提供VCO的控制电压。 控制电路对控制电路操作的分频器进行编程，以便在预定范围内改变分频器的除数，该预定范围由存储在存储器中的信息确定，所述存储器对应于要由接收机扫描和接收的频带中的频率范围。 在命令信号上，控制电路操作以将分频器的除数上变频或降低以使VCO的频率，从而接收机在给定方向上扫描，并且在信号被接收到除法器除数的变化时 接收机扫描终止。 VCO可以在频率上或向下扫描，并且扫描可以从频率范围的上（或下）端返回到下（或上）端，然后反转或从一端的重复扫描 范围向另一方向相同。 在所公开的优选实施例中，公开了一种多频带扫描接收机，其中存储的用于控制电路的信息对应于多个频带中的每一个的末端，对应于特定频带的信息被响应于接收频带的选择而被使用 通过频带切换装置。

公开(公告)号：US5729179A

公开(公告)日：1998-03-17

申请号：US718000

申请日：1996-09-26

申请人： Yasuaki Sumi

发明人： Yasuaki Sumi

IPC分类号： H03K23/66 ,  H03L7/087 ,  H03L7/197 ,  H03K21/00 ,  H03L7/18

CPC分类号： H03L7/1974 ,  H03K23/667 ,  H03L7/087

摘要： In a variable frequency divider capable of N+1/2 frequency division, a programmable frequency divider alternately frequency-divides an input signal by a frequency division ratio N (N being an integer) or by a frequency division ratio N+1. A first signal generating circuit generates a first signal in synchronism with an output signal of the programmable frequency division circuit. A second signal generating circuit generates a second signal which is identical to the first signal but delayed by half a period of the input signal. An output circuit alternately selects the first and second signals, and outputs the selected signal as frequency-divided signal. A delay circuit outputs a delayed signal identical to the first signal but delayed by one period of the input signal. A preset signal generating circuit alternately selects the delayed signal and the first signal, and presets the programmable frequency division circuit with the selected signal. The programmable frequency divider used may operate at the same speed as in N frequency division.

摘要翻译： 在具有N ++ E，1/2 + EE分频的可变分频器中，可编程分频器以分频比N（N为整数）或分频比交替地对输入信号进行分频 N + 1。 第一信号发生电路与可编程分频电路的输出信号同步地产生第一信号。 第二信号发生电路产生与第一信号相同但延迟输入信号的一半周期的第二信号。 输出电路交替地选择第一和第二信号，并将选择的信号作为分频信号输出。 延迟电路输出与第一信号相同但延迟输入信号的一个周期的延迟信号。 预置信号发生电路交替地选择延迟信号和第一信号，并且用所选择的信号预设可编程分频电路。 所使用的可编程分频器可以以与N分频相同的速度工作。

公开(公告)号：US4048570A

公开(公告)日：1977-09-13

申请号：US685343

申请日：1976-05-11

申请人： Yasuaki Sumi

发明人： Yasuaki Sumi

IPC分类号： H03J5/02 ,  H04B1/26

CPC分类号： H04B1/005 ,  H03J5/0272 ,  H04B1/26

摘要： A multiple-band superheterodyne receiver, comprising a high frequency amplifier for receiving a high frequency signal, a local oscillator for providing an oscillation frequency signal the frequency of which is different by a given frequency difference from the received high frequency signal, a mixer for mixing these two frequency signals for providing an intermediate frequency signal, a band selecting switch, and means for setting the data concerning the frequency of a high frequency signal to be received, said local oscillator comprising a voltage controlled oscillator for providing an oscillation frequency signal the frequency of which is variable as a function of a given control voltage, a frequency divider for frequency dividing the output from the voltage controlled oscillator, a read only memory for storing the data concerning a plurality of frequency differences, each corresponding to one of said plurality of receiving frequency bands and responsive to the band selecting signal for selectively withdrawing the data concerning the corresponding frequency difference of the selected band, means responsive to the read only memory and the high frequency setting means for varying the rate of frequency division of the frequency divider to a value determined by the frequency difference and the set high frequency, and a phase detector responsive to a reference oscillator and the frequency divider for providing a control voltage associated with the frequency of the output from the frequency divider to the said voltage controlled oscillator, whereby the intermediate frequency of the said receiver is adaptably changed in response to the band selecting switch, with the result that the difference in the intermediate frequency is compensated which is caused depending on the receiving band, the broadcasting standard, and the like.

公开(公告)号：US06894571B2

公开(公告)日：2005-05-17

申请号：US10250671

申请日：2002-01-15

申请人： Yasuaki Sumi ,  Norio Morimoto

发明人： Yasuaki Sumi ,  Norio Morimoto

IPC分类号： H03L7/08 ,  H03L7/087 ,  H03L7/089 ,  H03L7/095 ,  H03L7/191 ,  H03L7/193 ,  H03L7/197 ,  H03L7/00

CPC分类号： H03L7/087 ,  H03L7/0802 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/191 ,  H03L7/193 ,  H03L7/1974 ,  H03L2207/18

摘要： A PLL circuit comprises a reference signal generating unit for generating reference signals of different phases, variable frequency dividers for dividing the frequency of the output signal of a voltage-controlled oscillator (VCO) and thereby outputting feedback signals, and a phase comparator for comparing the phase of each feedback signal with that of the corresponding reference signal and thereby outputting phase comparison signals. When the output signal is synchronized with a preset frequency signal, at least one variable frequency divider of the variable frequency dividers is operated, and the operation of the other is stopped.

摘要翻译： PLL电路包括用于产生不同相位的参考信号的参考信号产生单元，用于分压压控振荡器（VCO）的输出信号的频率的可变分频器，从而输出反馈信号，以及相位比较器，用于比较 每个反馈信号的相位与相应参考信号的相位相反，从而输出相位比较信号。 当输出信号与预设频率信号同步时，可变分频器的至少一个可变分频器被操作，另一个的操作被停止。

公开(公告)号：US06522183B2

公开(公告)日：2003-02-18

申请号：US09888175

申请日：2001-06-22

申请人： Yasuaki Sumi

发明人： Yasuaki Sumi

IPC分类号： H03L706

CPC分类号： H03L7/191 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/107 ,  Y10S331/02

摘要： A PLL device has a voltage-controlled oscillator, a reference generator that generates reference signals with different phases, and a main divider that divides the frequency of the output signal of the voltage-controlled oscillator by a frequency-division ratio N1. An auxiliary divider divides the frequency of the output of the main divider by a frequency-division ratio N2. A distribution circuit distributes the output of the auxiliary divider as feedback signals. Phase detectors compare the reference signals and the feedback signals, and generate error signals. Each of the main divider and the auxiliary divider has a programmable divider or a counter. The main divider and the auxiliary divider are both operative during start-up to shorten PLL lock-up time, and the auxiliary divider then powers down to reduce power consumption.

摘要翻译： PLL器件具有压控振荡器，产生具有不同相位的参考信号的参考发生器，以及将压控振荡器的输出信号的频率除以分频比N1的主分压器。 辅助分频器将分频器的输出频率除以分频比N2。 分配电路将辅助分频器的输出分配为反馈信号。 相位检测器比较参考信号和反馈信号，并产生误差信号。 每个主分压器和辅助分频器都有一个可编程分频器或一个计数器。 主分压器和辅助分频器在启动期间都可以工作，以缩短PLL锁定时间，辅助分频器则关断以降低功耗。

公开(公告)号：US06853222B2

公开(公告)日：2005-02-08

申请号：US10262191

申请日：2002-10-01

申请人： Yasuaki Sumi

发明人： Yasuaki Sumi

IPC分类号： H03K23/66 ,  H03L7/087 ,  H03L7/089 ,  H03L7/091 ,  H03L7/191 ,  H03L7/23 ,  H03L7/06

CPC分类号： H03K23/665 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/191 ,  H03L7/23

摘要： A PLL circuit including a generating means (3) for generating a plurality of reference signals (fR1 to fR8) having mutually differing phases, a main frequency divider (30) dividing an output signal (fVCO) of a voltage-controlled oscillator (29) by a frequency-division ratio of N1, an auxiliary frequency divider (31) dividing an output (fV′) of the main frequency divider by a frequency-division ratio of N2, a distribution circuit (32) distributing an output (Q1a, Q2a, Q3a) of the auxiliary frequency divider as a plurality of feedback signals (fV1 to fV8), and phase comparators (12 to 19) comparing the reference signals with the feedback signals to output error signals (ER1 to ER8). Each of the main frequency divider and the auxiliary frequency divider is comprised of a variable frequency divider or a counter.

摘要翻译： 一种PLL电路，包括用于产生具有相互不同相位的多个参考信号（fR1至fR8）的发生装置（3），分压电压控制振荡器（29）的输出信号（fVCO）的主分频器（30） 通过N1的分频比，将主分频器的输出（fV'）除以N2的分频比的辅助分频器（31），分配输出（Q1a，Q2a）的分配电路（32） ，Q3a）作为多个反馈信号（fV1〜fV8），以及将参考信号与反馈信号进行比较以输出误差信号（ER1〜ER8）的相位比较器（12〜19）。 主分频器和辅助分频器分别由可变分频器或计数器组成。

公开(公告)号：US06670855B2

公开(公告)日：2003-12-30

申请号：US10067712

申请日：2002-02-05

申请人： Yasuaki Sumi

发明人： Yasuaki Sumi

IPC分类号： H03L700

CPC分类号： H03L7/0802 ,  H03L7/087 ,  H03L7/0898 ,  H03L7/191 ,  Y10S331/02

摘要： In a PLL device with a plurality of phase comparators, when one phase comparator has reached a locked state, this phase comparator is allowed to keep on delivering an output, while outputs of the other phase comparators are disabled. Accordingly, power consumption can be reduced. Furthermore, an error current output from a charge pump (109) connected to the phase comparators to output an error signal is reduced when lock approaches. Accordingly, lock failure can be avoided. Furthermore, a time constant of a low-pass filter (220) that receives the output of the charge pumps connected to the phase comparators is altered following alteration of the number of the phase comparators (212 to 219) that deliver their outputs. Accordingly, power consumption can be reduced, and also stability and converging speed are improved. Using distribution means (318) instead of frequency dividers provided for the phase comparators individually makes LSI implementation easy.

摘要翻译： 在具有多个相位比较器的PLL器件中，当一个相位比较器已经达到锁定状态时，允许该相位比较器继续输出输出，而其它相位比较器的输出被禁止。 因此，能够降低功耗。 此外，当锁接近时，从连接到相位比较器输出误差信号的电荷泵（109）输出的误差电流减小。 因此，可以避免锁定失败。 此外，接收连接到相位比较器的电荷泵的输出的低通滤波器（220）的时间常数在改变传送其输出的相位比较器（212至219）的数量之后改变。 因此，可以降低功耗，提高稳定性和收敛速度。 使用分配装置（318）而不是为相位比较器提供的分频器单独地使LSI实现变得容易。

公开(公告)号：US4088959A

公开(公告)日：1978-05-09

申请号：US682832

申请日：1976-05-04

申请人： Yasuaki Sumi

发明人： Yasuaki Sumi

IPC分类号： H03J7/18 ,  H03J5/02 ,  H03J7/28 ,  H04B1/26 ,  H04B1/32

CPC分类号： H04B1/005 ,  H03J5/0272 ,  H04B1/26

摘要： A frequency synthesized multi-band receiver having a phase locked loop (PLL) including a voltage controlled oscillator (VCO) for producing the local oscillator frequency. The PLL includes a programmable divider for dividing the output of the VCO for comparison with a reference frequency in a phase detector to produce a voltage for controlling the output frequency of the VCO. Memory means are provided for storing information concerning the upper and lower frequency limits of the bands over which the receiver is to operate.

摘要翻译： 一种具有锁相环（PLL）的频率合成多频带接收机，该锁相环包括用于产生本地振荡器频率的压控振荡器（VCO）。 PLL包括可编程除法器，用于将VCO的输出与相位检测器中的参考频率进行比较，以产生用于控制VCO的输出频率的电压。 提供存储装置用于存储关于接收机将在其上操作的频带的上限和下限频率的信息。

公开(公告)号：US06486741B2

公开(公告)日：2002-11-26

申请号：US09970734

申请日：2001-10-04

申请人： Yasuaki Sumi

发明人： Yasuaki Sumi

IPC分类号： H03L7087

CPC分类号： H03L7/191 ,  H03L7/087

摘要： A PLL circuit produces first to n-th (n being an integer equal to or greater than 2) reference signals. A first variable frequency divider divides the frequency of an output of a voltage-controlled oscillator to produce a first feedback signal. A second variable frequency divider divides the output of the voltage-controlled oscillator to produce second to n-th feedback signals. A phase comparator compares the phases of the first to the n-th reference signals with the phases of the first to the n-th feedback signals to produce first to n-th error signals. A controller produces a control signal from the error signals. The PLL circuit synchronizes the first reference signal with the first feedback signal in phase after the phase difference between at least one of the first to n-th reference signals and a corresponding feedback signal becomes smaller than a predetermined value. The frequency-division ratio of the second variable frequency divider is 1/n that of the first variable frequency divider.

摘要翻译： PLL电路产生第一至第n（n为等于或大于2的整数）参考信号。 第一可变分频器分压电压控制振荡器的输出的频率以产生第一反馈信号。 第二可变分频器分压电压控制振荡器的输出以产生第二至第n反馈信号。 相位比较器将第一至第n参考信号的相位与第一至第n反馈信号的相位进行比较，以产生第一至第n个误差信号。 控制器从误差信号产生控制信号。 PLL电路在第一至第n参考信号中的至少一个与相应的反馈信号之间的相位差变得小于预定值之后，将第一参考信号与第一反馈信号同相同步。 第二可变分频器的分频比是第一可变分频器的分频比为1 / n。

公开(公告)号：US6100767A

公开(公告)日：2000-08-08

申请号：US162094

申请日：1998-09-28

申请人： Yasuaki Sumi

发明人： Yasuaki Sumi

IPC分类号： H03K23/66 ,  H03K23/68 ,  H03L7/087 ,  H03L7/089 ,  H03L7/113 ,  H03L7/18 ,  H03L7/181 ,  H03L7/191 ,  H03L7/197 ,  H03L7/199 ,  H03L7/085

CPC分类号： H03L7/0891 ,  H03K23/665 ,  H03K23/68 ,  H03L7/087 ,  H03L7/113 ,  H03L7/18 ,  H03L7/181 ,  H03L7/191 ,  H03L7/199 ,  H03L7/1974

摘要： In a phase-locked loop with reference, feedback, and error signals, the trade-off between lock-up time and power dissipation is improved by one of the following methods: supplying a continuous error signal, instead of an intermittent error signal, to a charge pump during lock acquisition; employing a half-integer frequency divider and making multiple phase-and-frequency comparisons during each reference signal cycle; employing a prescaled feedback signal and making multiple phase-and-frequency comparisons during each reference signal cycle; providing multiple feedback loops and employing a selectable number of the loops during lock acquisition; and employing multiple feedback loops with prescaling of the reference and feedback signals.

摘要翻译： 在具有参考，反馈和误差信号的锁相环中，通过以下方法之一来提高锁定时间和功耗之间的权衡：将连续的误差信号而不是间歇性误差信号提供给 锁定采集期间的电荷泵; 采用半整数分频​​器，并在每个参考信号周期进行多次相位和频率比较; 采用预分频反馈信号，并在每个参考信号周期进行多次相位和频率比较; 在锁获取期间提供多个反馈回路并采用可选数量的循环; 并采用具有对参考和反馈信号进行预分频的多个反馈回路。