-
公开(公告)号：US20120146156A1
公开(公告)日：2012-06-14
申请号：US13396892
申请日：2012-02-15
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0629
摘要： A semiconductor device includes an MIS transistor and an electric fuse. The MIS transistor includes a gate insulating film formed on the semiconductor substrate, and a gate electrode including a first polysilicon layer, a first silicide layer, and a first metal containing layer made of a metal or a conductive metallic compound. The electric fuse includes an insulating film formed on the semiconductor substrate, a second polysilicon layer formed over the insulating film, and a second silicide layer formed on the second polysilicon layer.
摘要翻译： 半导体器件包括MIS晶体管和电熔丝。 MIS晶体管包括形成在半导体衬底上的栅极绝缘膜和包括第一多晶硅层，第一硅化物层和由金属或导电金属化合物制成的第一金属含有层的栅电极。 电熔丝包括形成在半导体衬底上的绝缘膜，形成在绝缘膜上的第二多晶硅层和形成在第二多晶硅层上的第二硅化物层。
-
2.发明授权公开(公告)号：US07518903B2
公开(公告)日：2009-04-14
申请号：US11712480
申请日：2007-03-01
IPC分类号： G11C11/00
CPC分类号： G11C7/12 , G11C5/148 , G11C7/20 , G11C7/22 , G11C7/222 , G11C11/5685 , G11C13/0007 , G11C13/0026 , G11C13/0038 , G11C2207/2227 , G11C2213/31 , G11C2213/79
摘要： In a semiconductor memory device including resistance change memory devices, when a resistance change memory device is in standby mode, the two terminals of the resistance change memory device, i.e., a bit line and a source line, are set at a precharge potential Vp, respectively. At the time of a set operation, the bit line is set to a set voltage Vd, which is higher than the precharge potential Vp, while the source line is grounded. At the time of a reset operation, bit line is grounded, while the source line is set to the set voltage Vd. At the time of a data-read operation, the source line is grounded by a read bias generation circuit, while the potential of the bit line is kept at the precharge potential Vp.
摘要翻译： 在包括电阻变化存储器件的半导体存储器件中，当电阻变化存储器件处于待机模式时，电阻变化存储器件的两个端子，即位线和源极线被设置为预充电电位Vp， 分别。 在设定操作时，位线被设定为高于预充电电位Vp的设定电压Vd，而源极线接地。 在复位操作时，位线接地，而源极线设置为设定电压Vd。 在数据读取操作时，源极线由读偏置产生电路接地，同时位线的电位保持在预充电电位Vp。
-
公开(公告)号：US07203117B2
公开(公告)日：2007-04-10
申请号：US11245075
申请日：2005-10-07
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： A fuse device and a program transistor are connected in series with each other. A flip-flop turns ON, in response to a start signal, the program transistor to start program of the fuse device. A 2-input NAND circuit outputs an end signal at a time point where change in a resistance value of the fuse device is increased to reach a predetermined level while monitoring change in the resistance value of the fuse device through change in a voltage at a junction point of the fuse device and the program transistor. The flip-flop turns OFF, in response to the end signal, the program transistor to automatically terminate the program of the fuse device. Thus, the resistance value of the fuse device is increased to the predetermined level in a minimum program time.
摘要翻译： 熔丝器件和程序晶体管彼此串联连接。 触发器响应于启动信号而导通，程序晶体管开始保险丝装置的编程。 2输入NAND电路在熔断器件的电阻值的变化增加以达到预定值的时间点输出结束信号，同时通过接点处的电压变化来监测熔丝器件的电阻值的变化 保险丝装置和程序晶体管的点。 触发器关闭，响应于结束信号，程序晶体管自动终止保险丝装置的程序。 因此，保险丝装置的电阻值在最小程序时间内增加到预定电平。
-
公开(公告)号：US07200025B2
公开(公告)日：2007-04-03
申请号：US11272818
申请日：2005-11-15
IPC分类号： G11C17/00
摘要： Selection signals output from a decoder are selectively set at High according to the states (blown or not blown) or fuses in bit cells in a cell group specifying circuit. Then, one of transistor gates is turned ON so that a data bit cell group in/from which data is written and read out is selected. Accordingly, stored data can be rewritten multiple times by sequentially blowing the fuses in the cell group specifying circuit.
摘要翻译： 从解码器输出的选择信号根据单元组指定电路中的位单元中的状态（发生或不发生）或熔丝选择性地设置为高。 然后，晶体管栅极中的一个导通，从而选择写入/读出数据的数据位单元组。 因此，可以通过在单元组指定电路中顺序吹送保险丝来重写多个存储的数据。
-
公开(公告)号：US20070070707A1
公开(公告)日：2007-03-29
申请号：US11526057
申请日：2006-09-25
IPC分类号： G11C11/34
CPC分类号： G11C16/0416 , G11C2216/10 , H01L27/105 , H01L27/11521 , H01L27/11558
摘要： A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate includes a plurality of MOS transistors sharing the floating gate. In the device, a PMOS is used for coupling during writing and an n-type depletion MOS (DMOS) is used for coupling during erasure. Coupling of channel inversion capacitance by the PMOS is used for writing and coupling of depletion capacitance by the n-type DMOS is used for erasure, thereby increasing the erase speed without increase of area, as compared to a conventional three-transistor nonvolatile memory element.
摘要翻译： 用于通过在浮动栅极中累积电荷来存储数据的非易失性半导体存储器件包括共享浮置栅极的多个MOS晶体管。 在器件中，在写入期间使用PMOS耦合并且在擦除期间使用n型耗尽MOS（DMOS）耦合。 与传统的三晶体管非易失性存储元件相比，通过PMOS将沟道反转电容耦合用于n型DMOS的耗尽电容的写入和耦合用于擦除，从而增加擦除速度而不增加面积。
-
公开(公告)号：US20070069803A1
公开(公告)日：2007-03-29
申请号：US11526060
申请日：2006-09-25
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A circuit includes a plurality of stages each including a MOS transistor and a capacitor of which one end is connected to one of a drain and a source of the MOS transistor. The plurality of stages are connected with each other by cascade connection of the MOS transistors. A gate of the MOS transistor is connected electrically to one of the drain and the source thereof in each stage, and a substrate for at least one pair of adjacent MOS transistors are connected electrically to one of the drain and the source of one of the pair. The back bias effect is suppressed, and the layout area is reduced. Further, a plurality of booster capacitors connected in series are provided in succeeding stages, thereby suppressing degradation of breakdown voltage of each capacitor.
摘要翻译： 电路包括多个级，每个级包括MOS晶体管和电容器，其一端连接到MOS晶体管的漏极和源极之一。 多个级通过MOS晶体管的级联连接而相互连接。 MOS晶体管的栅极在每个级中电连接到漏极和源极之一，并且用于至少一对相邻MOS晶体管的衬底电连接到该对之一的漏极和源极之一 。 背偏置效果被抑制，布局面积减小。 此外，在后续阶段提供串联连接的多个升压电容器，从而抑制每个电容器的击穿电压的劣化。
-
公开(公告)号：US07057956B2
公开(公告)日：2006-06-06
申请号：US10928366
申请日：2004-08-30
IPC分类号： G11C7/00
CPC分类号： G11C7/1096 , G11C7/062 , G11C7/1078
摘要： A semiconductor integrated circuit device includes: first and second nonvolatile memory elements; a first amplifier for amplifying an output signal from the first nonvolatile memory element to output the amplified signal; and a second amplifier for outputting to the first amplifier a control signal generated by amplifying an output signal from the second nonvolatile memory element. The second amplifier fixes the output signal from the first amplifier at a high potential or a low potential based on data stored in the second nonvolatile memory element.
摘要翻译： 一种半导体集成电路器件，包括：第一和第二非易失性存储元件; 第一放大器，用于放大来自第一非易失性存储器元件的输出信号以输出放大的信号; 以及第二放大器，用于向第一放大器输出通过放大来自第二非易失性存储元件的输出信号而产生的控制信号。 第二放大器基于存储在第二非易失性存储器元件中的数据，将来自第一放大器的输出信号固定在高电位或低电位。
-
8.发明申请公开(公告)号：US20060023538A1
公开(公告)日：2006-02-02
申请号：US11191963
申请日：2005-07-29
CPC分类号： G11C16/12
摘要： A semiconductor memory device includes: first and second bit cells for storing complementary data; a scan circuit for outputting a selected data signal; a bit-cell selector receiving the output of the scan circuit and selecting one of the bit cells; and a data write controlling circuit for controlling data writing. Write paths for all the bit cells for storing “0” are not selected and data is written only in a bit cell for storing “1”, so that write operation performed in steps is achieved.
摘要翻译： 半导体存储器件包括：用于存储互补数据的第一和第二位单元; 用于输出所选数据信号的扫描电路; 接收所述扫描电路的输出并选择所述位单元之一的位单元选择器; 以及用于控制数据写入的数据写入控制电路。 用于存储“0”的所有位单元的写入路径不被选择，并且数据仅被写入用于存储“1”的位单元中，从而实现了步骤执行的写入操作。
-
公开(公告)号：US08384466B2
公开(公告)日：2013-02-26
申请号：US13417548
申请日：2012-03-12
IPC分类号： H01H37/76
CPC分类号： H01L27/0207 , G11C17/18 , H01L23/5256 , H01L27/0288 , H01L27/10 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit.
摘要翻译： 半导体器件包括电熔丝电路和程序保护电路。 电熔丝电路包括串联连接在一起的一个熔丝元件和一个晶体管，并放置在一个程序电源和一个接地之间，以及控制部分。 程序保护电路与电熔丝电路并联在程序电源和接地之间。 当在程序电源和接地之间施加浪涌电压时，上述结构允许一部分浪涌电流可以流过程序保护电路。
-
公开(公告)号：US20110141825A1
公开(公告)日：2011-06-16
申请号：US13036327
申请日：2011-02-28
CPC分类号： G11C11/417 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C2029/0409 , G11C2029/5006
摘要： A semiconductor integrated circuit system comprises a semiconductor memory device including a memory cell array having a plurality of memory cells; a monitor circuit for monitoring characteristics of the memory cells; and a voltage output circuit connected to the semiconductor memory device to supply a power supply voltage to the semiconductor memory device; the voltage output circuit being configured to change an output voltage according to an output of the monitor circuit.
摘要翻译： 半导体集成电路系统包括具有多个存储单元的存储单元阵列的半导体存储器件; 用于监视存储器单元的特性的监视器电路; 以及电压输出电路，连接到半导体存储器件，以向半导体存储器件提供电源电压; 电压输出电路被配置为根据监视电路的输出来改变输出电压。
-
-
-
-
-
-
-
-
-
搜索结果
53 条记录 (耗时 0.017 秒)
