公开(公告)号：US5933364A

公开(公告)日：1999-08-03

申请号：US237853

申请日：1999-01-27

申请人： Yasuhiro Aoyama ,  Kiyoto Oota ,  Kazuhiko Shimakawa

发明人： Yasuhiro Aoyama ,  Kiyoto Oota ,  Kazuhiko Shimakawa

IPC分类号： H01L27/108 ,  G11C5/02 ,  G11C5/06 ,  G11C5/14 ,  G11C11/401 ,  H01L21/8242

CPC分类号： G11C5/14 ,  G11C5/025 ,  G11C5/063

摘要： A semiconductor device according to the present invention includes: a semiconductor chip; and memory and logic sections formed on the semiconductor chip. The memory section includes: an array of memory cells; a sense amplifier circuit; and memory interconnects respectively provided in a number n (where n is a positive integer) of interconnect layers. The logic section includes logic circuits having logic interconnects respectively provided in a number n+m (where m is a positive integer) of interconnect layers. A metal layer is formed in one of (n+1)th to (n+m)th interconnect layers, covers the array of memory cells and supplies a predetermined potential to the memory section.

摘要翻译： 根据本发明的半导体器件包括：半导体芯片; 以及形成在半导体芯片上的存储器和逻辑部分。 存储器部分包括：存储器单元阵列; 一个读出放大器电路; 和分别设置在n个（其中n是正整数））互连层的存储器互连。 逻辑部分包括逻辑电路，逻辑电路具有分别以互连层数n + m（其中m为正整数）提供的逻辑互连。 在（n + 1）至（n + m）个互连层之一中形成金属层，覆盖存储单元阵列并向存储部分提供预定电位。

公开(公告)号：US6122214A

公开(公告)日：2000-09-19

申请号：US273474

申请日：1999-03-22

申请人： Tomonori Fujimoto ,  Kiyoto Oota

发明人： Tomonori Fujimoto ,  Kiyoto Oota

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： In addition to a pulse train of a refresh request (RRQ) signal requesting for refresh per memory row, a self-refresh mode (SRMOD) signal is applied to a refresh control circuit. As soon as the SRMOD signal makes a transition from LOW to HIGH, an oscillation circuit starts generating a clock pulse train. In response to this clock pulse train, a set pulse is generated. A flip-flop circuit is set by the set pulse and a leading edge of a periodic refresh request (PRRQ) signal pulse is generated. Every time the PRRQ signal becomes HIGH, a reset pulse is generated, the flip-flop circuit is reset by the reset pulse, and a trailing edge of the PRRQ signal pulse is generated. Such arrangement provides a memory having a novel refresh input specification capable of reducing a burden of logic circuits for controlling access of the memory.

摘要翻译： 除了刷新请求（RRQ）信号的脉冲串之外，还请求刷新控制电路的自刷新模式（SRMOD）信号。 一旦SRMOD信号从低电平变为高电平，振荡电路开始产生时钟脉冲串。 响应该时钟脉冲串，产生设定脉冲。 触发器电路由设置脉冲设置，并且产生周期性刷新请求（PRRQ）信号脉冲的前沿。 每当PRRQ信号变为高电平时，产生复位脉冲，触发电路被复位脉冲复位，产生PRRQ信号脉冲的后沿。 这种布置提供具有新颖的刷新输入规范的存储器，其能够减少用于控制存储器访问的逻辑电路的负担。

公开(公告)号：US06628555B2

公开(公告)日：2003-09-30

申请号：US10218307

申请日：2002-08-15

申请人： Masataka Kondo ,  Kiyoto Oota ,  Tomonori Fujimoto ,  Yoshihiko Sumimoto

发明人： Masataka Kondo ,  Kiyoto Oota ,  Tomonori Fujimoto ,  Yoshihiko Sumimoto

IPC分类号： G11C2900

CPC分类号： G11C11/4074 ,  G11C8/08

摘要： A boosting circuit included in a semiconductor integrated circuit for efficiently stabilizing a boosted potential, including a plurality of boosting circuits and a timing control circuit for distributing the operations of the boosting circuits. Boosting operations per operating cycle of a memory increase in number so as to suppress a reduction in boosted source potential, the reduction being caused by consumption. Moreover, it is possible to perform a boosting operation in a time period equal to that of consuming boosted source potential, resulting in an efficient boosting operation.

摘要翻译： 包括在用于有效地稳定升压电位的半导体集成电路中的升压电路，包括多个升压电路和用于分配升压电路的操作的定时控制电路。 存储器的每个操作周期的升压操作数量增加，以便抑制增强的源极电位的降低，这是由消耗引起的。 此外，可以在与消耗升高的电位电位相同的时间段内进行升压操作，从而实现有效的升压操作。

公开(公告)号：US06493282B2

公开(公告)日：2002-12-10

申请号：US09946480

申请日：2001-09-06

申请人： Masahisa Iida ,  Kiyoto Oota ,  Yuji Yamasaki ,  Hakuhei Kawakami

发明人： Masahisa Iida ,  Kiyoto Oota ,  Yuji Yamasaki ,  Hakuhei Kawakami

IPC分类号： G11C700

CPC分类号： G11C7/10 ,  G11C2207/104

摘要： A semiconductor integrated circuit includes: a first n-well defined in a p-type semiconductor region; word lines; data lines; and a DRAM array. In the array, memory cells are arranged in matrix over the first n-well. Each memory cell includes a p-channel MOS access transistor and a capacitor. The access transistor has its gate connected to an associated one of the word lines, its source connected to an associated one of the data lines and its drain connected to the capacitor. The integrated circuit further includes: a row of sense amplifiers coupled to the data lines; a word line driver for driving the word lines; and a power supply circuit. The power supply circuit receives an external supply voltage, generates internal supply voltages by stepping down the external supply voltage and then applies the internal supply voltages to the sense amplifiers, word line driver and first n-well.

公开(公告)号：US06459643B2

公开(公告)日：2002-10-01

申请号：US09794771

申请日：2001-02-28

申请人： Masataka Kondo ,  Kiyoto Oota ,  Tomonori Fujimoto ,  Yoshihiko Sumimoto

发明人： Masataka Kondo ,  Kiyoto Oota ,  Tomonori Fujimoto ,  Yoshihiko Sumimoto

IPC分类号： G11C700

CPC分类号： G11C11/4074 ,  G11C8/08

摘要： A boosting circuit included in a semiconductor integrated circuit for efficiently stabilizing a boosted potential, including a plurality of boosting circuits and a timing control circuit for distributing the operations of the boosting circuits. Boosting operations per operating cycle of a memory increase in number so as to suppress a reduction in boosted source potential, the reduction being caused by consumption. Moreover, it is possible to perform a boosting operation in a time period equal to that of consuming boosted source potential, resulting in an efficient boosting operation.

摘要翻译： 包括在用于有效地稳定升压电位的半导体集成电路中的升压电路，包括多个升压电路和用于分配升压电路的操作的定时控制电路。 存储器的每个操作周期的升压操作数量增加，以便抑制增强的源极电位的降低，这是由消耗引起的。 此外，可以在与消耗升高的电位电位相同的时间段内执行升压操作，从而实现有效的升压操作。

公开(公告)号：US06349072B1

公开(公告)日：2002-02-19

申请号：US09705541

申请日：2000-11-03

申请人： Kenichi Origasa ,  Kiyoto Oota ,  Tomonori Fujimoto

发明人： Kenichi Origasa ,  Kiyoto Oota ,  Tomonori Fujimoto

IPC分类号： G11C800

CPC分类号： G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/409 ,  G11C2207/2281 ,  G11C2207/229

摘要： To realize a semiconductor memory which can be operated at a low frequency without reducing a data transfer rate, the semiconductor memory according to the invention is configured so that a series of operation can be finished in two clock cycles of row address strobe operation and column address strobe operation for operating DRAM. Timing for turning a sense amplifier activation signal SE at a high level after delay time determined by a first delay element since a leading edge of a clock pulse CLK that turns a row address strobe pulse (/RAS) at a low level and activating a sense amplifier sequence is generated. Also, timing for starting read operation and write operation since a leading edge of the clock pulse CLK at which a column address strobe pulse (/CAS) is turned at a low level, turning the sense amplifier activation signal SE at a low level, turning a bit line precharge signal EQPR at a high level and starting precharge operation when the termination of reading and writing is detected is acquired.

摘要翻译： 为了实现能够以低频率操作而不降低数据传输速率的半导体存储器，根据本发明的半导体存储器被配置为使得可以在行地址选通操作和列地址的两个时钟周期中完成一系列操作 频闪操作用于操作DRAM。 用于在由第一延迟元件确定的延迟时间之后将读出放大器激活信号SE转换为高电平的时序，因为将行地址选通脉冲（/ RAS）变为低电平并激活感测的时钟脉冲CLK的前沿 产生放大器序列。 此外，从列位地址选通脉冲（/ CAS）转为低电平的时钟脉冲CLK的前沿开始读操作​​和写操作的定时，将读出放大器激活信号SE转为低电平，转动 获取高电平的位线预充电信号EQPR和检测到读取和写入结束时的开始预充电操作。