公开(公告)号：US5283455A

公开(公告)日：1994-02-01

申请号：US911582

申请日：1992-07-10

申请人： Yasuo Inoue ,  Tadashi Nishimura ,  Motoi Ashida

发明人： Yasuo Inoue ,  Tadashi Nishimura ,  Motoi Ashida

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/786 ,  H01L29/76 ,  H01L27/01 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/6675 ,  H01L29/66765 ,  H01L29/78624 ,  H01L29/78642

摘要： An upper insulating layer is formed on an upper surface of a gate electrode formed on an insulating substrate. A gate insulating layer is formed on sidewalls of the gate electrode and the surfaces of the upper insulating layer. A semiconductor layer is formed on the surfaces of the gate insulating layer. Three source/drain regions are formed in the semiconductor layer. Two independent channel regions are formed in the semiconductor layer along both side surfaces of the gate electrode. Source/drain regions are arranged on both ends of two channel regions. Each source/drain region has an LDD structure formed in a self alignment manner by an oblique ion implantation method and a vertical ion implantation method using sidewall insulating layers formed on the channel regions as masks.

摘要翻译： 在绝缘基板上形成的栅电极的上表面上形成上绝缘层。 栅极绝缘层形成在栅电极的侧壁和上绝缘层的表面上。 在栅极绝缘层的表面上形成半导体层。 在半导体层中形成三个源/漏区。 沿着栅电极的两个侧表面在半导体层中形成两个独立的沟道区。 源极/漏极区域布置在两个沟道区域的两端。 每个源极/漏极区域具有通过倾斜离子注入方法以自对准方式形成的LDD结构和使用在沟道区上形成的侧壁绝缘层作为掩模的垂直离子注入方法。

公开(公告)号：US5382807A

公开(公告)日：1995-01-17

申请号：US192761

申请日：1994-02-07

申请人： Kazuhito Tsutsumi ,  Motoi Ashida ,  Yasuo Inoue

发明人： Kazuhito Tsutsumi ,  Motoi Ashida ,  Yasuo Inoue

IPC分类号： H01L21/336 ,  H01L21/8244 ,  H01L21/8247 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66765 ,  H01L27/1108 ,  H01L29/78621 ,  Y10S257/903

摘要： A structure of a thin film transistor capable of reducing the power consumption in the waiting state and stabilizing the data holding characteristic in application of the thin film transistor as a load transistor in a memory cell in a CMOS-type SRAM is provided. A gate electrode is formed of a polycrystalline silicon film on a substrate having an insulating property. A gate insulating film is formed on the gate electrode. A polycrystalline silicon film is formed on the gate electrode with the gate insulating film interposed therebetween. Source/drain regions including a region of low concentration and a region of high concentration are formed in one and another regions of the polycrystalline silicon film separated by the gate electrode. Thus, the thin film transistor is formed. The thin film transistor is applied to p-channel MOS transistors serving as load transistors in a memory cell of a CMOS-type SRAM. P-channel MOS transistors are connected to n-channel MOS transistors serving as driver transistors in the memory cell. The n-channel MOS transistors are formed in a p-type well region, and the p-channel MOS transistors are formed on an interlayer insulating film on the n-channel MOS transistors.

摘要翻译： 提供了一种薄膜晶体管的结构，其能够在CMOS型SRAM中的存储单元中降低等待状态下的功耗并稳定作为负载晶体管的薄膜晶体管的数据保持特性。 栅电极由具有绝缘性的基板上的多晶硅膜形成。 在栅电极上形成栅极绝缘膜。 在栅极上形成多晶硅膜，栅极绝缘膜插入其间。 在由栅电极分离的多晶硅膜的一个和另一个区域中形成包括低浓度区域和高浓度区域的源极/漏极区域。 因此，形成薄膜晶体管。 薄膜晶体管被施加到用作CMOS型SRAM的存储单元中的负载晶体管的p沟道MOS晶体管。 P沟道MOS晶体管连接到用作存储单元中的驱动晶体管的n沟道MOS晶体管。 n沟道MOS晶体管形成在p型阱区中，并且p沟道MOS晶体管形成在n沟道MOS晶体管的层间绝缘膜上。

公开(公告)号：US08174062B2

公开(公告)日：2012-05-08

申请号：US12504146

申请日：2009-07-16

申请人： Motoi Ashida

发明人： Motoi Ashida

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/105 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4234

摘要： A semiconductor memory device includes: a semiconductor substrate; a first impurity region; a second impurity region; a channel region; a first gate formed on a main surface on a side of the first impurity region; a second gate formed on the main surface on a side of the second impurity region, with a second insulating film being interposed; and a third insulating film formed on a side surface of the first gate. An interface between the third insulating film and the semiconductor substrate directly under the third insulating film is located above an interface between the second insulating film and the main surface of the semiconductor substrate directly under the second insulating film. The total number of steps can thus be reduced, and lower cost is achieved.

摘要翻译： 半导体存储器件包括：半导体衬底; 第一杂质区; 第二杂质区; 一个通道区域 形成在所述第一杂质区一侧的主表面上的第一栅极; 第二栅极，形成在第二杂质区一侧的主表面上，第二绝缘膜被插入; 以及形成在所述第一栅极的侧表面上的第三绝缘膜。 第三绝缘膜和直接位于第三绝缘膜下方的半导体衬底之间的界面位于第二绝缘膜正下方的第二绝缘膜和半导体衬底的主表面之间的界面之上。 因此可以减少步骤的总数，并且实现更低的成本。

公开(公告)号：US07816207B2

公开(公告)日：2010-10-19

申请号：US12719524

申请日：2010-03-08

申请人： Tsutomu Okazaki ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

发明人： Tsutomu Okazaki ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

摘要翻译： 半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点 绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。 第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤 的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。

公开(公告)号：US07709874B2

公开(公告)日：2010-05-04

申请号：US11649208

申请日：2007-01-04

申请人： Tsutomu Okazaki ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

发明人： Tsutomu Okazaki ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

IPC分类号： H01L29/94

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

摘要翻译： 半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点 绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。 第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤 的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。

公开(公告)号：US07348637B2

公开(公告)日：2008-03-25

申请号：US11376142

申请日：2006-03-16

申请人： Motoi Ashida ,  Takashi Terada

发明人： Motoi Ashida ,  Takashi Terada

IPC分类号： H01L29/72

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including plural CMOS transistors with first and second transistors sharing a common first gate electrode and third and fourth transistors sharing a common second gate electrode that is adjacent and parallel to the first gate electrode. The first and third transistors share a common n-type channel MOS region and the second and fourth transistors share a common p-type channel MOS region. The semiconductor device has a wire connecting the n-type channel MOS region and the p-type channel MOS region. The wire has a width greater than a distance between the first and second adjacent gate electrodes, and a portion of the wire is disposed right above a portion of at least one of the first and second gate electrodes with an insulating film interposed therebetween.

摘要翻译： 一种包括多个CMOS晶体管的半导体器件，其中第一和第二晶体管共享共同的第一栅电极，第三和第四晶体管共享与第一栅电极相邻并平行的公共第二栅电极。 第一和第三晶体管共享共同的n型沟道MOS区，第二和第四晶体管共享公共p型沟道MOS区。 半导体器件具有连接n型沟道MOS区和p型沟道MOS区的导线。 所述导线的宽度大于所述第一和第二相邻栅电极之间的距离，并且所述导线的一部分设置在所述第一和第二栅电极中的至少一个的一部分的正上方，其间插入绝缘膜。

公开(公告)号：US20080070358A1

公开(公告)日：2008-03-20

申请号：US11980603

申请日：2007-10-31

申请人： Motoi Ashida

发明人： Motoi Ashida

IPC分类号： H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/76897 ,  H01L21/823842 ,  H01L21/823871

摘要： Manufacturing of semiconductor device includes forming, at substrate main surface, PMOS and NMOS regions separated by PN film. Polysilicon is formed at surface. First insulating film serves as gate insulating film. Second insulating film is formed on polysilicon surface, in gate electrode region extending from PMOS to NMOS regions across PN film. Polysilicon layer is patterned with second insulating film, and first gate electrode extends from PMOS region surface to PN and second gate electrode extends from NMOS region to PN connecting to first gate electrode. At main surface, opposed first source and drain regions are formed by placing first gate electrode therebetween in plan view. At main surface, opposed second source and drain regions are formed by placing second gate electrode therebetween in plan view. The second insulating film, covering first and second gate electrodes is patterned and exposed on PN. Exposed first and second gate electrodes are silicidized.

公开(公告)号：US20060180872A1

公开(公告)日：2006-08-17

申请号：US11376142

申请日：2006-03-16

申请人： Motoi Ashida ,  Takashi Terada

发明人： Motoi Ashida ,  Takashi Terada

IPC分类号： H01L29/76

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including plural CMOS transistors with first and second transistors sharing a common first gate electrode and third and fourth transistors sharing a common second gate electrode that is adjacent and parallel to the first gate electrode. The first and third transistors share a common n-type channel MOS region and the second and fourth transistors share a common p-type channel MOS region. The semiconductor device has a wire connecting the n-type channel MOS region and the p-type channel MOS region. The wire has a width greater than a distance between the first and second adjacent gate electrodes, and a portion of the wire is disposed right above a portion of at least one of the first and second gate electrodes with an insulating film interposed therebetween.

公开(公告)号：US20120069638A1

公开(公告)日：2012-03-22

申请号：US13188088

申请日：2011-07-21

申请人： Ryoji MATSUDA ,  Motoi Ashida ,  Takaharu Tsuji

发明人： Ryoji MATSUDA ,  Motoi Ashida ,  Takaharu Tsuji

IPC分类号： G11C11/02 ,  G11C7/00

CPC分类号： G11C29/028 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/021

摘要： A semiconductor device which it can accommodate variations in a write current threshold in each memory cell and can secure a write margin is provided. An MRAM device includes an MTJ memory cell arranged in a matrix, plural bit lines each arranged corresponding to a memory cell column, plural digit lines each arranged corresponding to a memory cell row, and a write current adjusting unit which adjusts a current amount of a write current to be flowed through a bit line and/or a digit line, in order to perform a data write to each MTJ memory cell normally. The write current adjusting unit divides the plural bit lines and/or the plural digit lines into units of at least one write current line as division units, and includes plural write current adjusting circuits which adjust the current amount of write current in each of the division units.

摘要翻译： 提供了可以适应每个存储器单元中的写入电流阈值的变化并且可以确保写入裕度的半导体器件。 MRAM装置包括以矩阵形式布置的MTJ存储单元，对应于存储单元列排列的多个位线，对应于存储单元行排列的多个数字线，以及调整当前量的一个写入电流调整单元 写入要流过位线和/或数字线的电流，以便正常地对每个MTJ存储器单元执行数据写入。 写入电流调整单元将多个位线和/或多个数字线分成至少一个写入电流线的单位作为分割单元，并且包括多个写入电流调节电路，其在每个分割中调整当前的写入电流量 单位。

公开(公告)号：US07939448B2

公开(公告)日：2011-05-10

申请号：US12888995

申请日：2010-09-23

申请人： Tsutomu Okazaki ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

发明人： Tsutomu Okazaki ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

IPC分类号： H01L21/311

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

摘要翻译： 半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点 绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。 第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤 的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。